UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer dreamertom
Observer
2,239 Views
Registered: ‎06-16-2017

When should I assert reset and gt_reset in the Aurora 11.0 10B/8B core design ?

Jump to solution

Hi,

 

I am uncertain that when should I assert reset and gt_reset. My design runs a 2.5GT aurora link between two boards through a SFP based optical fiber. If the reset/gt_reset being asserted only once when powering up, there will be CRC errors detected on the rx_side of the earlier configured board, but no errors in the later board. Then if I assert reset/gt_reset again after channel_up asserted first, the link would be stable and no CRC errors would be detected on the both sides.
So when I should assert reset/gt_reset to avoid CRC errors? Should I assert them when the channel_up is low by pulling off the fiber or reconfiguring another board?
Thanks a lot.
IDE: Vivado 2016.1

IP: Aurora 8/10b:V11.0;
PS: SFP is connected to a XC7K325T, and it is enabled by FPGA pulling down the level of TX_DISABLE pin(it is pulled up by a resistance).

0 Kudos
1 Solution

Accepted Solutions
3,952 Views
Registered: ‎01-08-2012

Re: When should I assert reset and gt_reset in the Aurora 11.0 10B/8B core design ?

Jump to solution

There's a whole section on resets in UG476 chapter 2.  You really need to read (and follow) this closely, as Xilinx aren't joking about the requirements.

 

As you've found, a single reset at power-on isn't sufficient to ensure that the system works.  UG476 table 2-32 lists "Recommended Resets for Common Situations."

This includes conditions such as "Remote Power-Up" and "After Connecting RXN/RXP" which in this context means that the SFP presence and signal detect pins should drive the Rx reset (i.e. active when the SFP is absent or has Loss Of Signal).

 

Allan

0 Kudos
1 Reply
3,953 Views
Registered: ‎01-08-2012

Re: When should I assert reset and gt_reset in the Aurora 11.0 10B/8B core design ?

Jump to solution

There's a whole section on resets in UG476 chapter 2.  You really need to read (and follow) this closely, as Xilinx aren't joking about the requirements.

 

As you've found, a single reset at power-on isn't sufficient to ensure that the system works.  UG476 table 2-32 lists "Recommended Resets for Common Situations."

This includes conditions such as "Remote Power-Up" and "After Connecting RXN/RXP" which in this context means that the SFP presence and signal detect pins should drive the Rx reset (i.e. active when the SFP is absent or has Loss Of Signal).

 

Allan

0 Kudos