UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Adventurer
Adventurer
678 Views
Registered: ‎03-31-2017

Where is the 10G Ethernet MAC simulation model?

[moved from the simulation forum]

 

Anyone know how to locate and compile the 10G Ethernet MAC simulation models, for 2015.4, and Riviera-PRO 2016.10, and preferably VHDL?

 

Building the core generates 3 VHDL files for the behavioural model: mac_base_sync_resetn.vhd, mac_base_block.vhd, and mac_base.vhd. However, mac_base_block.vhd instantiates 'mac_base_core_top', which I can't find anywhere. It's not in any of the IP output products, or in the 2015.4 installation directories, or in unisims.

 

If I instead use the simulation netlist (mac_base_sim_netlist.vhdl) decryption fails. The Verilog code appears to have the encrypted core, but decryption fails on one of the two Verilog files (mac_base_core.v), but not on ten_gig_eth_mac_v15_0_rfs.v (they have *different* Aldec keynames?!)

 

Thanks.

0 Kudos
2 Replies
Xilinx Employee
Xilinx Employee
648 Views
Registered: ‎05-01-2013

Re: Where is the 10G Ethernet MAC simulation model?

Please try doing simulation from Vivado first

1. Generate IP core example design

2. Select "Target Simulator" as "Riviera-Pro"

3. Click run simulation

When you're able to run the simulation, copy the simulation command lines generated by Vivado tool.

You can use them in Riviera-Pro directly next time.

0 Kudos
Adventurer
Adventurer
630 Views
Registered: ‎03-31-2017

Re: Where is the 10G Ethernet MAC simulation model?

Hi - sorry, not getting notifications of replies, for some reason.

 

I hadn't tried simulating an example design from the GUI, but that looks useful. Unfortunately, it doesn't help.

 

1 - Vivado hangs up when you run the simulation. 'ps ax | grep -i riviera' shows

 

/bin/sh /home/eda/aldec/Riviera-PRO-2016.10-x64/bin/../runvsimsa -l compile.log -do do {mac_base_demo_tb_compile.do}

 

which might be the problem; "-do do {mac_base_demo_tb_compile.do} " isn't valid syntax and will drop Riviera out to a command prompt. But ps has probably just dropped the double quotes around the -do "...", which would be a valid command.

 

2 - The library.cfg in this directory (where mac_base_demotb_compile.do is) is incomplete - it doesn't map unisims, so the do file errors out, which might also explain why Vivado hangs.

 

3 - If I add the unisims mapping the do file then errors out when it tries to compile mac_base_sim_netlist.vhdl, because it can't decrypt it, which is exactly the problem I had to start with. So, back to square #1.

 

Summary: (1) there doesn't appear to be a behavioural simulation model. (2) There's only an encrypted netlist. (3) The encrypted netlist has the wrong key in it, and Riviera 2016.10 can't decrypt it. (4) Other encrypted Xilinx IP in 2015.4 *does* have the correct Riviera key in it, but 10G MAC model doesn't.

0 Kudos