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Observer
Observer
480 Views
Registered: ‎02-08-2019

Why does 100G ethernet subsystem have gt_rx and gt_tx pins?

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Take a look at this clip from a block diagram:

whyisgttxhere.png

 

 

 

 

 

 

 

 

 

 

 

There is an output port on the 100G ethernet subsystem called "gt_tx", and there is also one on the left-hand side called "gt_rx".

From what I understand, these have to connect to the Generalized Transcievers in the FPGA. So, of course, I started trying to figure out how to assign the pin! 

But as it turns out, if you just run the implementation, then this happens:

whoconnectedthis.png

It seems that the proper connections are already made. Right?

So why is that gt_tx output port there on the IP core? Do I have to use it in the pin assignments?

 

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Moderator
Moderator
428 Views
Registered: ‎04-01-2018

Hi @mahkoe 

If the core is implemented with the default values in the UI, then GT tx and rx will be getting tx and rx locations which are selected in the CMAC/GT Selection and Configuration TAB. 

For Example:

cmac_config.png

 

The GT tx and rx connections are visible out side to override the with GT placements mentioned in the UI when assigned with locations manually in the xdc. But assignments should be in accordance with CMAC region GT lines to be assigned and the clocking need to be inline with the GT requirements. 

For more details please refer PG203 (Integrated 100G Ethernet v2.685 PG203 May 22, 2019) Page 85,86 (Transceiver Selection Rules).

 

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1 Reply
Highlighted
Moderator
Moderator
429 Views
Registered: ‎04-01-2018

Hi @mahkoe 

If the core is implemented with the default values in the UI, then GT tx and rx will be getting tx and rx locations which are selected in the CMAC/GT Selection and Configuration TAB. 

For Example:

cmac_config.png

 

The GT tx and rx connections are visible out side to override the with GT placements mentioned in the UI when assigned with locations manually in the xdc. But assignments should be in accordance with CMAC region GT lines to be assigned and the clocking need to be inline with the GT requirements. 

For more details please refer PG203 (Integrated 100G Ethernet v2.685 PG203 May 22, 2019) Page 85,86 (Transceiver Selection Rules).

 

-----------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------------

View solution in original post