Hi, I'm trying to make a simple 10GBASE-SR design with my VC707 board. I wanna know if I have to choose 'Shared Logic Included in Example Design" or "Shared Logic Included in Core"
Shared logic in core means transceiver quad pll, reference clock buffer and some rest logic are included in core however in shared logic in example those are outside the core.
Core provides example design for your reference, right click on .xci file and select open example design.
For better understanding, generate example designs for both shared logic in core and shared logic in example.