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Explorer
Explorer
2,715 Views
Registered: ‎11-05-2008

XAPP1305: petalinux 2018.2 ?

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Hi,

  I am trying to port my design from Vivado 2017.3 to 2018.2, but the ethernet interface stops working.

 

  The design is based on the XAPP1305 example (ps_emio_eth_1g).

 

  So I have moved back to XAPP1305 design and I tried the same porting, but with same results:

  ethernet interface doesn't become ready.

 

  In both projects , I have changed the design so that PCS/PMA is configured to have a 156.25 reference clock

  which is the default for the source si570 component on board.

 

  Is there an updated 2018.2 xapp1305 stuff? Is someone in Xililnx working on it?

 

Luca

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1 Solution

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Xilinx Employee
Xilinx Employee
1,875 Views
Registered: ‎08-15-2018

Re: XAPP1305: petalinux 2018.2 ?

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Hi @tim_k,

Finger crossing is always a great place to start ;)

 

I believe the reason you are seeing the of_phy_connect() failed error is because the zcu102 images by default reprogram the si570 to 148.5MHz:

148mhzRefClk.PNG

You can fix this by adding the following node to your system-user.dtsi (This configuration is for a 156.25MHz ref clock):

&i2c1 {
    status = "okay";
    clock-frequency = <400000>;
    i2c-mux@74 { /* u34 */
        compatible = "nxp,pca9548";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x74>;
        i2c@3 { /* i2c mw 74 0 8 */
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <3>;
            si570_2: clock-generator3@5d {
                #clock-cells = <0>;
                compatible = "silabs,si570";
                reg = <0x5d>;
                temperature-stability = <50>;
                factory-fout = <156250000>;
                clock-frequency = <156250000>;
            };
        };
    };
};

I would also double check that the following settings are set in petalinux-config -c kernel:

  • Device Drivers > Network device support > PHY Device support and infrastructure > <*>Drivers for xilinx PHYs
  • Device Drivers > DMA Engine Support > < > Xilinx AXI DMAS Engine

 

I've verified that this setup works on my ZCU102 here:

zcu102plptp.jpg

 

pingWorking.PNG

 

For your convenience, I've packaged up my 2018.2 project Vivado bd.tcl, petalinux .bsp, and some ready-to-test SD images. It's too large to attach here, but if you PM me I can send it to you. It's the same as the XAPP1305/6 design, just upgraded to 2018.2 and with the above changes.

 

Hope this helps!

 

Thanks,

Clayton

18 Replies
Explorer
Explorer
2,697 Views
Registered: ‎04-26-2017

Re: XAPP1305: petalinux 2018.2 ?

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Hello @colombini_luca,

 

I had the same problem and I coudn't solve that. Hope this threat will find the solution. 

 

Best regards,

 

baldrism

Moderator
Moderator
2,651 Views
Registered: ‎08-25-2009

Re: XAPP1305: petalinux 2018.2 ?

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Hi @colombini_luca,

 

Could you please upload your complete Linux bootlog to have a look?

We do have plans to upgrade XAPP1305/1306 to 2018.x and the work is in progress. But there isn't a final release date yet.

"Don't forget to reply, kudo and accept as solution."
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Explorer
Explorer
2,647 Views
Registered: ‎11-05-2008

Re: XAPP1305: petalinux 2018.2 ?

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Hi @nanz,

 

   here is my linux boot log.

 

Luca

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Explorer
Explorer
2,562 Views
Registered: ‎11-05-2008

Re: XAPP1305: petalinux 2018.2 ?

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Hi @nanz,

 

   Have you replicated the issue on ethernet connection with 2018.2?

 

   Please see my next post about a possible issue in the design:

  https://forums.xilinx.com/t5/Networking-and-Connectivity/Auto-Negotiation-Vector-value-for-1G-2-5-Geth-PCS-PM-in-XAPP1305/m-p/899920/highlight/true#M14462

 

   Let me know your feedback.

 

Thanks,

Luca

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Explorer
Explorer
2,556 Views
Registered: ‎11-05-2008

Re: XAPP1305: petalinux 2018.2 ?

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Hi @nanz,

 

   I am using the official ZCU102 2018.2 BSP (xilinx-zcu102-v2018.2-final.bsp).

 

   Should I get a different BSP for the XAPP1305 design to work?

 

Thanks,

Luca

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Participant rhickey
Participant
2,291 Views
Registered: ‎01-19-2016

Re: XAPP1305: petalinux 2018.2 ?

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Hi @colombini_luca,

We struggled with this for awhile but now have it working.

My understanding is that the clock frequency should be 125 MHz and that 156.25 will not work.  Using 2018.2, we had problems that the design could not change the frequency on the si570 from its default of 156.25 to the required 125MHz.  Instead we changed the default frequency of the si570 to 125MHz using the SCUI tool.  (see below link for some gotchas with that tool)

https://forums.xilinx.com/t5/Evaluation-Boards/ZCU106-SCUI-is-not-working/td-p/874519

Additionally we were trying to use SGMII instead of 1000BASE-X.  We were unable to get the reference design for SGMII working and needed to use 1000BASE-X.  We are still working with Xilinx to debug.

Once we used 1000BASE-X with a default si570 frequency of 125 MHz, we got ethernet to work.  We are using a ZCU106 board but not much different for the ZCU102.

(By the way, you made need to make changes to your system-user.dtsi.  I am not currently able to share our changes but if you still have problems ping me back ...)

Roger

 

 

 

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Observer jbeck695
Observer
2,098 Views
Registered: ‎05-22-2018

Re: XAPP1305: petalinux 2018.2 ?

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Are there any updates on when xapp1305 will be released for 2018.2 or 2018.3?

We have zcu102 board & have been trying to get it working with 10g ethernet but keep running into deadends. Currently have 2018.2 on vivado, sdk & petalinux side but based on design docs of xapp1305 only being available for 2018.1 I'm about to download 2018.1 vivado & continue to work thru whether issue is with PHY, si570 frequency, system-user.dtsi, or something else altogether?

Thx for any feedback,

Joe

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Participant tim_k
Participant
2,003 Views
Registered: ‎06-27-2018

Re: XAPP1305: petalinux 2018.2 ?

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I am in very much the same boat. I've tried to get the PL 1G reference design to build in 2018.3 and 2018.2 and the validation step fails:

[BD 41-238] Port/Pin property FREQ_HZ does not match between /clk_wiz_0/clk_in1(74992500) and /zynq_ps/zusp_ps/pl_clk0(74992508)
[BD 41-238] Port/Pin property FREQ_HZ does not match between /axi_eth_0/ref_clk(50000000.0) and /clk_wiz_0/clk_out1(49995005)

Because of the reference clock is 33.330 MHz, the processor PLL can't make exactly 75.00 MHz (or 50.00), so the clk_wiz can't make exactly 50.00MHz from the 74.992500.

I can change the clk_wiz input clock freq paramete, but it can't make 50.000, so the second check still fails. I can see the parameter in the pcs_pma block in the axi_eth_0 block, but it's read only so I can't change it.

Interestingly, 2018.1 has exactly the same clock frequencies, but does not complain.

I've built with 2018.1 successfully, but only have petalinux 2018.2 and 2018.3. Neither of which will  find with the 2018.1 created ethernet port. Built with the version appropriate zcu102 bsp's they can't find the PHY. So now I'm downloading/installing petalinux 2018.1 and crossing my fingers.

 

Xilinx, please get this straightened out!

-Tim.

Participant tim_k
Participant
1,934 Views
Registered: ‎06-27-2018

Re: XAPP1305: petalinux 2018.2 ?

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It appears finger crossing is not a good debug strategy.

Building the reference design from the provided scripts, with 2018.1 Vivado and Petalinux, did not yield an entirely successful build. As previously mentioned, I don't get the clock errors and Vivado completes the build without error. I also built the petalinux image with 2018.1, using the zcu102 2018.1 BSP. Petalinux built with no problems, but the Xilinx driver could not communicate with the PHY:  

xilinx_axienet 80000000.ethernet: of_phy_connect() failed

Which happens to be the same error I got when trying the 2018.1 built bitstream with a 2018.2/3 petalinux.

So I tried rebuilding the Petalunux image using the BSP provided in the XAPP1305 files (software/bsps/pl_eth_1g/pl_eth_1g.bsp) - and it works! The interface comes up, and I am able to ping my laptop from the board.

So, this begs the question - what's different between the two BSPs? The petalinux tools have a way to package up a BSP for distribution. Is there a way to unpack one to see what's inside? I thought it might be a zip file, but unzipping errors out with unknownt file type.

Does anyone have any suggestions?

 

-Tim

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Xilinx Employee
Xilinx Employee
1,876 Views
Registered: ‎08-15-2018

Re: XAPP1305: petalinux 2018.2 ?

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Hi @tim_k,

Finger crossing is always a great place to start ;)

 

I believe the reason you are seeing the of_phy_connect() failed error is because the zcu102 images by default reprogram the si570 to 148.5MHz:

148mhzRefClk.PNG

You can fix this by adding the following node to your system-user.dtsi (This configuration is for a 156.25MHz ref clock):

&i2c1 {
    status = "okay";
    clock-frequency = <400000>;
    i2c-mux@74 { /* u34 */
        compatible = "nxp,pca9548";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x74>;
        i2c@3 { /* i2c mw 74 0 8 */
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <3>;
            si570_2: clock-generator3@5d {
                #clock-cells = <0>;
                compatible = "silabs,si570";
                reg = <0x5d>;
                temperature-stability = <50>;
                factory-fout = <156250000>;
                clock-frequency = <156250000>;
            };
        };
    };
};

I would also double check that the following settings are set in petalinux-config -c kernel:

  • Device Drivers > Network device support > PHY Device support and infrastructure > <*>Drivers for xilinx PHYs
  • Device Drivers > DMA Engine Support > < > Xilinx AXI DMAS Engine

 

I've verified that this setup works on my ZCU102 here:

zcu102plptp.jpg

 

pingWorking.PNG

 

For your convenience, I've packaged up my 2018.2 project Vivado bd.tcl, petalinux .bsp, and some ready-to-test SD images. It's too large to attach here, but if you PM me I can send it to you. It's the same as the XAPP1305/6 design, just upgraded to 2018.2 and with the above changes.

 

Hope this helps!

 

Thanks,

Clayton

Adventurer
Adventurer
1,732 Views
Registered: ‎06-14-2018

Re: XAPP1305: petalinux 2018.2 ?

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Anyone tried 10G PL axi ethernet using Petalinux 2018.3? Does it work? Thank you.

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Observer ahira
Observer
1,561 Views
Registered: ‎10-15-2018

Re: XAPP1305: petalinux 2018.2 ?

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@claytonc 

 

I would love to get your project file as well, if you don't mind sharing. Anyway you can send it to me?

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Contributor
Contributor
685 Views
Registered: ‎06-05-2018

Re: XAPP1305: petalinux 2018.2 ?

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is it working now?

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Participant tim_k
Participant
672 Views
Registered: ‎06-27-2018

Re: XAPP1305: petalinux 2018.2 ?

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I've had it working in 2018.3 and 2019.1. Not the reference design directly, but designs based on it. The same rules apply, you have to include the I2C clock fix in your system-user.dtsi, and make sure the kernel is configured with the correct drivers (DMA, Phy).

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Contributor
Contributor
652 Views
Registered: ‎06-05-2018

Re: XAPP1305: petalinux 2018.2 ?

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hello @tim_k ,

thanks for your help.

is ti possible to share the system user please?

thank you very much.

 

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Participant tim_k
Participant
636 Views
Registered: ‎06-27-2018

Re: XAPP1305: petalinux 2018.2 ?

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The changes are dependent on what board you're using, but essintially what was already posted by claytonr above. You'll have to adjust if your on MPSoC or RFSoC or your own board.

 

-Tim.

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475 Views
Registered: ‎07-23-2019

Re: XAPP1305: petalinux 2018.2 ?

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Dear Sir,

Can you share your XAPP1305 pl_1g_ethernet , tcl and ready to test to me?

I use zcu102 with Vivado 2018.3/2018.2.

I have no idea where am I wroung with the XAPP1305 workflow.

Always linux boot with "eth0: link is not ready"

Many thanks.

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Participant tim_k
Participant
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Registered: ‎06-27-2018

Re: XAPP1305: petalinux 2018.2 ?

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If you're running 2018.3, you can just download the xapp1305 files (search xapp1305 on the Xilinx site, it's the first result), and build according to the instructions in the app note, but make the system-user.dtsi changes as claytonr described above. At that point, you'll have a copy of what I started with, and it works.  If the build in ready_to_test/linux/pl_ethernet_1g/ doesn't work, you've got other issues. It works withot modifications.

 

-Tim

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