cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Visitor
Visitor
2,811 Views
Registered: ‎09-22-2009

XAUI backplane communication problems (ML605 <-> ML555)

Hi,

 

currently I try to set up a backlane communication via XAUI between a ML555 and ML605. Therefor I have a small PCB with two PCIe x8 connectors where the boards are plugged. I use the first 4 lanes of PCIe connectors to establish the links. The 156.25 MHz clocks are also deliverd from the small PCB over the PCIe connectors.

The XAUI link comes up fine (no Local Faults, Alignment ok, Link Status ok) on both boards. Then I send on the ML605 a start frame with data (xgmii_txc <= X"01", xgmii_txd <= X"00000000000000FB"), after that some data frames and than a termination frame (xgmii_txc <= X"FF", xgmii_txd <= X"07070707070707FD"). On the ML555 i observe xgmii_rxc and xgmii_txd via ChipScope. Mostly I get what I expected. But somtimes it fails. Error case is as follows:

 

1. xgmii_rxc = X"1F", xgmii_rxd = X"000000FB07070707" - looks like it is shifted by 32 bits

2. data frame also shifted by 32 bits

3. xgmii_rxc = X"F0", xgmii_rxd = X"070707FDxxxxxxxx" - termination frame also shifted by 32 bits (the small x stands for data that I have send)

 

What can cause such an instable behavior. Can anybody help?

 

 

Thanks,

bebork

0 Kudos
1 Reply
Highlighted
Xilinx Employee
Xilinx Employee
2,621 Views
Registered: ‎04-06-2010

I believe this is normal behavior. The reason the interface behaves this way is because the XGMII interface is supposed to be a 32-bit interface DDR. Since you're using the internal XGMII, you essentially have two 32-bit interfaces making a 64-bit interface.

Hope this helps.
0 Kudos