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Adventurer
Adventurer
2,798 Views
Registered: ‎05-24-2013

XPS_LL_TEMAC 2.03a GMII Transmit Clock BUFG instantiated?

Hello,

 

I am working with the xps_ll_temac core on the Spartan-6 lx75 FPGA on an RGMII project. On 1 Gigabit mode, the design works until a certain temperature(50 C) and above it, it crashes. In the parameters of the core, I have the parameter "C_INCLUDE_IO" set to 0. Reading the manual of xps_ll_temac 2.03a, I see that with this parameter set to 0, BUFGs are not instantiated. My RGMII logic uses the The GMII_TX_CLK_0 that comes out of the xps_ll_temac to drive the ODDR2s. Hence I need a BUFG on that clock. 

 

My question is: With C_INCLUDE_IO set to 0, does the xps_ll_temac drive the GMII_TX_CLK_0 through a BUFG or without the BUFG?

 

Thanks,

Berk

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Adventurer
Adventurer
2,770 Views
Registered: ‎05-24-2013

Re: XPS_LL_TEMAC 2.03a GMII Transmit Clock BUFG instantiated?

Now I have left C_INCLUDE_IO as 0 and placed a BUFG on the clock coming from xps_ll_temac manually(highlighted in green):

 

RGMII_Clocking_Scheme.png

 

I have placed the manually inserted BUFG on the upper halve of the BUFG site, since its driving a non-clock load pin(inverter). Is this correct?

 

Also I get the following warning from the ISE 14.7(actually an error, but I have the CLOCK_DEDICATED_ROUTE=FALSE on the BUFGMUX):

 

WARNING:Place:1137 - This design is not guaranteed to be routable! This design
contains a global buffer instance,
<MICROBLAZE_INST/Soft_TEMAC/Soft_TEMAC/SOFT_SYS.I_TEMAC/GMII0.I_CLOCK_INST_0/
V6V5V4S6.BUFGMUX_SPEED_CLK>, driving the net, <MICROBLAZE_INST/gmii_clk>,
that is driving the following (first 30) non-clock load pins.
< PIN:
MICROBLAZE_INST/gmii_to_rgmii_0/gmii_to_rgmii_0/bufg_soft_temac_gmii_clk.I0;
>
This is not a recommended design practice in Spartan-6 due to limitations in
the global routing that may cause excessive delay, skew or unroutable
situations. It is recommended to only use a BUFG resource to drive clock
loads. Please pay extra attention to the timing and routing of this path to
ensure the design goals are met. This is normally an ERROR but the
CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN
<MICROBLAZE_INST/Soft_TEMAC/Soft_TEMAC/SOFT_SYS.I_TEMAC/GMII0.I_CLOCK_INST_0/
V6V5V4S6.BUFGMUX_SPEED_CLK.O> allowing your design to continue. This
constraint disables all clock placer rules related to the specified COMP.PIN.

 

So it complains about the BUFGMUX in the xps_ll_temac core. And it says that it is driving the BUFG Input pin, which is a non-clock load. Assuming that my understanding is correct, I don't know what to do in this case. The design routes to the end but I don't like this warning, Is there another way to do this? 

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