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patocarr
Teacher
Teacher
184 Views
Registered: ‎01-28-2008

Xapp1305 PL 10G fails to link on custom hardware

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Hi folks,

  I've run xapp1305 with the PL 10G after porting it to Vivado 2020.2 on the ZCU102 successfully. However, in the custom hardware, the clock fails to lock. The main difference between platforms is that the reference clock needs to be programmed (Si570 over I2C) after the PL is configured, and I suspect the GT is still failing to be reset properly. This is shown in the AR#71100 "10G/25G Ethernet Subsystem - GT QPLL reset is only issued at device configuration when the core is configured for multiple lanes or rate switching".

  Following this lead, I modified FSBL to a) program the Si570 XO over I2C and b) reset the newly added qpllreset_in port in the Ethernet IP using a GPIO. This is suggested in this post resetting the qpllreset_in port after the clock is set. I can verify the clock is set to the proper rate 156.25 MHz and the qpllreset_in is toggling properly.

  I have also updated the AXI DMA IP and changed it to the AXI MCDMA IP.

  However, none of these changes have made a difference. Even from Linux, I can program the Si570 and toggle the GT QPLL using the same GPIO, and bringing the link up and down. The driver still reports "XXV MAC block lock not complete" message, and reading the STAT_RX_BLOCK_LOCK_REG shows this bit is clear, i.e. no lock.

xapp1305 block design with MCDMA & GPIO on qpllreset_inxapp1305 block design with MCDMA & GPIO on qpllreset_in

  Any ideas how to proceed and/or debug this further?

Thanks in advance,

-Pat

 

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patocarr
Teacher
Teacher
162 Views
Registered: ‎01-28-2008

Folks,

  I fixed the issue with the ported design. The IP was wrongly configured to use a different MGT bank. The MCDMA IP did not get detected by the Linux driver however, so reverting to the AXI DMA fixed this as well.

Thanks,

-Pat

 

Give kudos if helpful. Accept as solution if it solves your problem.
https://tuxengineering.com/blog

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patocarr
Teacher
Teacher
163 Views
Registered: ‎01-28-2008

Folks,

  I fixed the issue with the ported design. The IP was wrongly configured to use a different MGT bank. The MCDMA IP did not get detected by the Linux driver however, so reverting to the AXI DMA fixed this as well.

Thanks,

-Pat

 

Give kudos if helpful. Accept as solution if it solves your problem.
https://tuxengineering.com/blog

View solution in original post

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