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Visitor ianas
Visitor
6,034 Views
Registered: ‎06-29-2016

Xilinx 10BASE-R PHY Latency [Virtex7]

Hi,

 

Could please somebody explain, as I could not figure out, what is the extra functionality in Xilinx 10G PHY that causes ~20 cycles of latency on both RX and TX sides? I mean, excluding the GTH, according the documentation. 64/66 coding is done by the GTH, scrambling/descrambling should take 1 cycle... so I'm a bit puzzled, what else is happening there.

 

Thanks!

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4 Replies
Visitor ianas
Visitor
5,961 Views
Registered: ‎06-29-2016

Re: Xilinx 10BASE-R PHY Latency [Virtex7]

Well... Anyone? :)

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Moderator
Moderator
5,909 Views
Registered: ‎02-16-2010

Re: Xilinx 10BASE-R PHY Latency [Virtex7]

Are you referring to GT wizard design?
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Visitor ianas
Visitor
5,860 Views
Registered: ‎06-29-2016

Re: Xilinx 10BASE-R PHY Latency [Virtex7]

No, the 10gig pcs/pma core (http://www.xilinx.com/products/intellectual-property/10gbase-r.html). It looks like excluding the GTH delay it takes ~150ns to process a single transfer word for the pcs/pma pipeline. I know that there are lower latency solutions, so I'm curious what takes so "long" for the Xilinx one.

 

I've started to experiment with naked GTH and custom scrambler/coder, but I haven't got far yet for various reasons.

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Xilinx Employee
Xilinx Employee
5,500 Views
Registered: ‎02-06-2013

Re: Xilinx 10BASE-R PHY Latency [Virtex7]

Hi

 

Please refer page 5 of below doc to know the blocks implemented in the fabric.

 

The elastic buffer,64b66b encoding, scrambler all add up to the latency caused though the core

 

http://www.xilinx.com/support/documentation/ip_documentation/ten_gig_eth_pcs_pma/v6_0/pg068-ten-gig-eth-pcs-pma.pdf

Regards,

Satish

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