06-29-2016 10:24 AM
Could please somebody explain, as I could not figure out, what is the extra functionality in Xilinx 10G PHY that causes ~20 cycles of latency on both RX and TX sides? I mean, excluding the GTH, according the documentation. 64/66 coding is done by the GTH, scrambling/descrambling should take 1 cycle... so I'm a bit puzzled, what else is happening there.
07-01-2016 10:54 AM
07-02-2016 04:00 PM
No, the 10gig pcs/pma core (http://www.xilinx.com/products/intellectual-property/10gbase-r.html). It looks like excluding the GTH delay it takes ~150ns to process a single transfer word for the pcs/pma pipeline. I know that there are lower latency solutions, so I'm curious what takes so "long" for the Xilinx one.
I've started to experiment with naked GTH and custom scrambler/coder, but I haven't got far yet for various reasons.
07-12-2016 02:32 AM
Please refer page 5 of below doc to know the blocks implemented in the fabric.
The elastic buffer,64b66b encoding, scrambler all add up to the latency caused though the core