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Visitor
Visitor
1,116 Views
Registered: ‎06-06-2018

Xilinx JESD204 and ADI DAC

Hello,

 

I am using a simple design just to test the JESD204B link establishment with Kintex-7 FPGA and AD9172 Dual link DAC. I have validated the design in the Vivado which says that there are no errors. I am using the Xilinx JESD204B IP (JESD204 v7.2). I am configuring the JESD204B IP as transmitter and I am generating this JESD204B core along with JESD204 PHY that means the core is implemented with physical as well as data link layer which can be seen in the figure below. I am also including the RPAT and JSPAT test pattern generator blocks in this core.

L = Number of lanes per link = 4

M = 2

F = 2

K =32

Transceiver Type = GTXE2

Line Rate = 6.25 Gbps

Reference Clock (MHz) = 156.25 MHz

PLL Type = CPLL

DRP Clock Frequency = 100

 

I intend to send the PRBS test patterns over the links i.e. txp and txn as shown in the figure. I am referring to the JESD204 v7.2 Product Guide for this project. It says that we can configure it in test mode by changing the register values as mentioned in the guide. I am also setting up the VCCO as 2.5 volts in the constraints file as it is mentioned in the FPGA datasheet for using the differential input/output pairs. 

 

Questions:

1)How to change the values of these registers to enable the transmission of PRBS test patterns?

2)Also, I am just connecting the non AXI ports for now. So will this thing work or do we have to connect the AXI ports such as s_axi and s_axi_tx to the AXI interconnect blocks which are then controlled by the Microblaze processor?

3)I am connecting the txp and txn output ports to the SERDES input ports on the DAC. SYSREF and SYNC signals are provided by the DAC evaluation board as the output which I have connected to the JESD204 IP block as inputs to the tx_sysref and tx_sync respectively using the Utility Buffers. I am also providing the ref_clk_p and ref_clk_n inputs with a reference clock which is generated using a clock source from DAC board. I am providing s_axi_clk with 100 MHz clock using the clocking wizard as shown in the figure. I am wondering whether the connections made are right or not?

 

I am sharing the block design as well as the block diagram for AD9172 for your reference. I am not able to establish the JESD204B link between FPGA and DAC. I am not concerned with the SPI programming through the FPGA for now as I am configuring the DAC using ADI software. I am configuring the DAC with same LMFS configuration as mentioned above. I am utilizing a single link and hence I have connected SYNC0 signal to the JESD204 IP block which is required for DAC0 as we can see from the block diagram. I would appreciate any help on this problem.

 

Regards,

 

Loukik Pingle

 

Block Design.jpg

 

 

 

AD9172-fbl.png

 

 

 

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Moderator
Moderator
1,036 Views
Registered: ‎02-16-2010

1. Can you connect locked output from MMCM to JESD core after inverting the signal?

2. Have you matched L,M,F,C parameters with DAC setting?

3. If you are referring to "Test Modes" register at 0x018 offset, it does not require AXIS interface signals connected at the IP interface.

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