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Xilinx Employee
Xilinx Employee
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Registered: ‎03-09-2011

Xilinx® Training on Connectivity

How to Design a Xilinx Connectivity System in 1 Day - Updated December 2013

This workshop introduces you to fundamental connectivity concepts and techniques for implementation in Xilinx FPGAs. The focus is on fundamental aspects of serial transceivers, PCIe® technology, memory interfaces, and Ethernet MACs. Design examples and labs show components from the Connectivity Targeted Reference Design (TRD). In addition, an IBERT lab is available that highlights usage of the serial transceivers. - Read More


PCIe Protocol Overview - Released March 2011

This course focuses on the fundamentals of the PCI Express® protocol specification. The typical PCIe® architecture, including data space, data movement, and the most commonly used Transaction Layer Packets (TLPs) are covered. Interrupts and error handling are also discussed. Implementation issues are covered in the two-day Designing a LogiCORE PCI Express System course. - Test Your Knowledge


Designing a LogiCORE PCI Express System - Updated October 2012

Attending the Designing a LogiCORE PCI Express System will provide you a working knowledge of how to implement a Xilinx PCI Express core in your applications. This course focuses on the implementation of a Xilinx PCI Express system within the Connectivity Targeted Reference Design (TRD). With this experience, you can improve your time to market with your PCIe core design. Various Xilinx PCI Express core products will be enumerated to aid you in selecting the proper solution. This course focuses on the AXI streaming interconnect. - Test Your Knowledge


Designing with Multi-Gigabit Serial I/O - Updated July 2013

Learn how to employ serial transceivers in your 7 series FPGA design. Understand and utilize the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection. Additional topics include use of the 7 Series FPGAs Transceiver Wizard, synthesis and implementation considerations, board design as it relates to the transceivers, and test and debugging. This course combines lectures with practical hands-on labs. - Test Your Knowledge


Designing with Ethernet MAC Controllers - Updated December 2011

Become acquainted with the various solutions that Xilinx offers for Ethernet connectivity. Learn the basics of the Ethernet standard, protocol, and OSI model while applying Xilinx solutions via hands-on laboratory exercises. Perform simulation to understand fundamental principles and obtain the knowledge to assess hardware design considerations and software development requirements. - Test Your Knowledge


Signal Integrity and Board Design for Xilinx FPGAs - Updated March 2013

Learn when and how to apply signal integrity techniques to high-speed interfaces between Xilinx FPGAs and other components. This comprehensive course combines design technique and methodology with relevant background concepts of high-speed bus and clock design, including transmission line termination, loading, and jitter. - Test Your Knowledge


How to Design a High-Speed Memory Interface - Updated October 2013

This course teaches hardware designers who are new to high-speed memory I/O to design a memory interface in Xilinx FPGAs. It introduces designers to the basic concepts of high-speed memory I/O design, implementation, and debugging using 7 series FPGAs. Additionally, you will learn about the tools available for high-speed memory interface design, implementation, and debugging.


Play Video 7-Series Dedicated Hardware
This video introduces the dedicated hardware resources available in the 7-Series FPGAs. The features described include the dedicated Serial Gigabit Transceivers, PCI Express core, and XADC resources.

Updated: Sept 2012
Play Video Reducing System Power & Cost with Artix-7 FPGAs
In this video you will learn about overall system power and cost with Artix-7 FPGAs. We’ll quickly review the Artix-7 FPGA architecture, logic fabric, 4th gen DSP48E1 slice, 6.6 Gbps GTP transceivers, PCIe Gen2 hard block, memory interface, analog interface, applications overview, and where you can learn more.

Released: Feb 2013