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Observer sabraosn
Observer
858 Views
Registered: ‎06-04-2018

Xilinx Vivado 2017.2 10G/25G Ethernet Subsystem IP core is different in multiple projects

I am new to Vivado and I am checking the code written by someone else. I seem to face a rather strange problem.

 

The Vivado version is 2017.2.1. The IP core which causes the problem is the 10G/25G Ethernet subsystem, VLNV is 'xilinx.com:ip:xxv_ethernet:2.2'.

 

IPCore_Compare.jpg

 

In this project, I don't see a port named 'gt_serial_port' for the Ethernet subsystem as shown by the left side of the image. The right side of the image is the Ethernet IP from another example project running on Vivado 2017.2.1. Both these designs have been obtained by clicking on 'IP Catalog' within the project and then searching for the xxv_ethernet IP core. AFAIU, since I click on the IP core which is offered by Xilinx, shouldn't both the designs be the same? How can I check from where these designs come from if it is not from Xilinx.

 

I face an issue in the project Tcl script because it searches for the 'gt_serial_port' which is not existent according to the image. Any help is appreciated.

 

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4 Replies
Moderator
Moderator
799 Views
Registered: ‎11-09-2017

Re: Xilinx Vivado 2017.2 10G/25G Ethernet Subsystem IP core is different in multiple projects

Hi @sabraosn

 

If you click on gt_serial_port (right side image), it contains gt_txp_out, gt_txn_out, gt_rxp_in, gt_rxn_in.

 

Click on gt_tx, gt_rx (left side image) it also contains same ports as gt_serial_port, they both are same.

 

Kindly attach the tcl scripts.

Regards
Pratap

Please mark the Answer as "Accept as solution" if information provided is helpful.

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Explorer
Explorer
499 Views
Registered: ‎05-22-2008

Re: Xilinx Vivado 2017.2 10G/25G Ethernet Subsystem IP core is different in multiple projects

I've run across this exact problem, when I exported a block diagram design, and then subsequently recreated it in another project. I can see that gt_serial_port contains both pairs of differential lines, but aside from that, what are these different? I've verified every option in the gui's are the same.

I'm running vivado 2018.1 and both designs use xxv_ethernet 2.4. 

When did this change occur? The information that @rpr added, where is this documented?

 

And most importantly, how do I reconnect these? In the block diagram, I am unable to drag and drop a connection. I presume this is because the the gt_tx and gt_rx ports are 2 pins, and the gt_serial port is 4 pins, without any sort of 2 pairs of 2 pins hierarchy

 

 

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Explorer
Explorer
478 Views
Registered: ‎05-22-2008

Re: Xilinx Vivado 2017.2 10G/25G Ethernet Subsystem IP core is different in multiple projects

So, digging in some, gt_rx and gt_tx are interfaces of type xilinx.com:display_xxv_ethernet:gt_ports:2.0

gt_serial_port is of type xilinx.com:interface:gt_rtl:1.0

So, how do I connect these? I'm pretty opposed to tunneling gt_serial_port all the way to my top level.

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Adventurer
Adventurer
148 Views
Registered: ‎08-07-2014

Re: Xilinx Vivado 2017.2 10G/25G Ethernet Subsystem IP core is different in multiple projects

@sabraosn,

 

I came across this problem just now and, googling around, found your post.

The problem arises on which "device" is used in the project. If the ZCU102 board is choosed, the 10G/25G Ethernet Subsystem IP is instantiated without the gt_rx port. If part xcu9eg-ffvb1156-2-e (the ZCU102's ZynqMP SoC) is choosed, gt_rx port will be available.

If that answer your question, please mark as solution and click in Kudos, please.

 

regards

Brasilino