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Contributor
Contributor
333 Views
Registered: ‎05-24-2018

ZC706 - Constraints for reference clock

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Hello, 

I am trying to run the 10G ethernet subsystem example design but I am having some issues with setting the right constraints. First off, I connected a counter controlled by 'coreclk' to an led, but that didn't work. Since the coreclk is controlled by the refclk_p/n, I tried to connect the reference clocks from the bank 111 on the transceiver block, but that failed (I think I connected the wrong clock). I tried to connect the userclk_p to the refclk_p since it generated the frequency that I needed, however, the bitstream failed to generate. I am now thinking of connecting the SMA reference clocks. That means I need to connect some external clock to them first right? I am a bit lost as to how to go about constraining the refclk_p in the top example design to the SMA and then to the userclk, since anything connected to the usrclk_p fails at the "generate bitstream" step. 

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Contributor
Contributor
192 Views
Registered: ‎05-24-2018

Re: ZC706 - Constraints for reference clock

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Hello @guozhenp ,

Thanks a lot for the help. I went on which what you suggested and figured out a way around it. I don't know if that was what you meant but here it goes. 

I connected the system 200MHz oscillator to the INPUT (sys_clk_p/n) ports and then through a clock wizard,  I generated a 156.25MHz clock using the MMCM option. I then passed this output clock through an OBUFDS and sent the differential outputs back to the OUTPUT (refout_p/n) to a user SMA (p/n) and then from there back to the INPUT (refclkin_p/n) through another user SMA (p/n) on the board. Now, the question is, why did I have to take a clock source from the output and send it back again (especially when there is another clock providing this same exact value)? Well, it's because the SMA input ports ensure clock integrity. If you want to feed an external clock to your design, you have to use the MGT_SMA differential ports. The output clock can go anywhere. I learned this is very important. 

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Xilinx Employee
Xilinx Employee
316 Views
Registered: ‎05-01-2013

回复: ZC706 - Constraints for reference clock

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Is this "userclk_p" your design output signal?

refclk_p/n are for GT reference clock. They can only be connected to an IBUFDS_GTE. And then the single output of the IBUFDS_GTE may be connected to a BUFG_GT

Please use the BUFG_GT output to your clock output.

Contributor
Contributor
307 Views
Registered: ‎05-24-2018

回复: ZC706 - Constraints for reference clock

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Hello @guozhenp 

 userclk_p/n are the programmable user clock ports on the board. In the design, the refclk_p/n are connected to the IBUFDS_GTE you mentioned (one of the sub-ips). That is not the issue. The issue is that I need to connect an external clock to the SMA ports on the GT that will feed the refclk_p/n ports. I want to use the differential output from a PLL to the SMA ports on the GT. Perhaps I did not get you well, can you please elaborate more on your answer?

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Xilinx Employee
Xilinx Employee
300 Views
Registered: ‎05-01-2013

回复: ZC706 - Constraints for reference clock

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I'm reading ZC706 User Guide

https://www.xilinx.com/support/documentation/boards_and_kits/zc706/ug954-zc706-eval-board-xc7z045-ap-soc.pdf

Do you mean to usrclk_p/n with 156.25MHz? However this clock is not for GT. GT needs the specified location reference clock input.

Contributor
Contributor
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Registered: ‎05-24-2018

回复: ZC706 - Constraints for reference clock

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Yes. That is the clock I am talking about. So, I need a PLL output to the SMA inputs on the GT. How do I do this? As a newbie, I was thinking of drawing the clock output from the userclk_p/n. I didn't know that should not be done. I understand that in order to control the GT, I need to connect an input clock to the specified inputs (FMC or SMA ports). So now the problem is whether to insert a PLL output into the design so that I can connect it to the SMA_REFCLK inputs of the GT. How can I do that? I already tried inserting a clock wizard from the IP catalog into the rtl. But implementation fails. 

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Xilinx Employee
Xilinx Employee
285 Views
Registered: ‎05-01-2013

回复: ZC706 - Constraints for reference clock

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As my understanding, these GT reference clock inputs are the specified ports on the board.

So you need to fly the line or connect the SMA cable outside to provide the clock on board.

There's no way to change the design inside to get the clock.

Contributor
Contributor
283 Views
Registered: ‎05-24-2018

回复: ZC706 - Constraints for reference clock

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Yes please. That is what I have been saying. Since they are fixed at the SMA_REFCLK (P/N) I need an input to them. The issue is how to get the input from the system PLL into my RTL. You mentioned using IBUFs. Can you please confirm if I understood well? 

System_CLK >> IBUFxx_xxxx >> clk_wiz >> output >> SMA reference clk Input >> core ? I am not sure of this connection but that is what I get from what you said. I may be wrong. Could you please elaborated more? 

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Xilinx Employee
Xilinx Employee
280 Views
Registered: ‎05-01-2013

回复: ZC706 - Constraints for reference clock

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The GT reference clock should be from the external differential clock with the specified port directly.

Because GT needs a high quality clock to work.

I'm afraid that the clock generated by the internal PLL is not good enough for GT to work.

Contributor
Contributor
193 Views
Registered: ‎05-24-2018

Re: ZC706 - Constraints for reference clock

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Hello @guozhenp ,

Thanks a lot for the help. I went on which what you suggested and figured out a way around it. I don't know if that was what you meant but here it goes. 

I connected the system 200MHz oscillator to the INPUT (sys_clk_p/n) ports and then through a clock wizard,  I generated a 156.25MHz clock using the MMCM option. I then passed this output clock through an OBUFDS and sent the differential outputs back to the OUTPUT (refout_p/n) to a user SMA (p/n) and then from there back to the INPUT (refclkin_p/n) through another user SMA (p/n) on the board. Now, the question is, why did I have to take a clock source from the output and send it back again (especially when there is another clock providing this same exact value)? Well, it's because the SMA input ports ensure clock integrity. If you want to feed an external clock to your design, you have to use the MGT_SMA differential ports. The output clock can go anywhere. I learned this is very important. 

View solution in original post

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