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Contributor
Contributor
1,662 Views
Registered: ‎03-23-2018

ZCU102 Aurora 64b66b Design Example: RX/TX from quad 128, reference clock from quad 129

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Hi All,

 

I am using Vivadi 2017.4 on ZCU102.

 

I tried to synthesize Aurora 64b66b Example Design with RX/TX from quad 128 with GT reference clock from quad 129.

 

However, IP GUI only allow me to use reference clock 0 or 1 from quad 128.

 

Is there any way change ref clk to quad129?

 

Thanks

Andrew

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1 Solution

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Moderator
Moderator
1,900 Views
Registered: ‎02-16-2010

Re: ZCU102 Aurora 64b66b Design Example: RX/TX from quad 128, reference clock from quad 129

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RTL code is not required to be modified. Have you done the following check after updating REFCLK constraint to point to quad 129?

1. open implemented design
2. Search for IBUFDS_GTE4 in the design
3. create a schematic for the IBUFDS_GTE4 instance which connects to Aurora IP
4. Check the connectivity of inputs and outputs of this IBUFDS_GTE4 primitive
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7 Replies
Xilinx Employee
Xilinx Employee
1,594 Views
Registered: ‎03-30-2016

Re: ZCU102 Aurora 64b66b Design Example: RX/TX from quad 128, reference clock from quad 129

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Hello @andrewngo

 

Unfortunately, this is the known limitation of Aurora 64B66B GUI. There is no plan for now, to update the GUI.
The workaround should be to select GT outside configuration and customize the GT Wizard instance inside the example design.

 

Best regards

Leo

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Moderator
Moderator
1,576 Views
Registered: ‎02-16-2010

Re: ZCU102 Aurora 64b66b Design Example: RX/TX from quad 128, reference clock from quad 129

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You can put the refclk location constraint to point to quad 129 with GT location set to quad 128. Vivado will automatically route the clock to quad 128.
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Contributor
Contributor
1,573 Views
Registered: ‎03-23-2018

Re: ZCU102 Aurora 64b66b Design Example: RX/TX from quad 128, reference clock from quad 129

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@karnanl


- If I create Aurora64b66b inside BD, the option "Generate Aurora without GT" will be gray out (disable).
- I manage to make Aurora64b66b Example Design working, but I want to use it inside BD.
- Not like Example Design, Aurora64b66b IP inside BD is not rtl code, so I cannot manually change refclock

- Transceiver Wizard is not BD friendly, so even I can make it, it is outside of BD, how can I connect it to Aurorra IP inside BD?

 

@venkata
- I did tried what you suggested: change mgtrefclk from quad 128 to quad129 but it doesn't work 'cuz gt wizard hard coded to quad128. So it is needed but not enough.
- I managed to change gt wizard instance RTL code to use "gtnorthrefclk" then it worked.

 

- I am still trying to find any work around, but so far could not find any way :(

 

Thank you all
Andrew

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Moderator
Moderator
1,569 Views
Registered: ‎02-16-2010

Re: ZCU102 Aurora 64b66b Design Example: RX/TX from quad 128, reference clock from quad 129

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Do you get any critical warning when you try to change the refclk location constraint? If it is, can you please share it?
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Xilinx Employee
Xilinx Employee
1,483 Views
Registered: ‎03-30-2016

Re: ZCU102 Aurora 64b66b Design Example: RX/TX from quad 128, reference clock from quad 129

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Hello @andrewngo

 

I see, so you are using BD/IPI. So, please don't "Generate Aurora without GT" and do not modify Aurora IP manually. ( you will have to do a lot of modification)

Advice from @venkata should work for your case.

 

Thanks
Leo

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Contributor
Contributor
1,474 Views
Registered: ‎03-23-2018

Re: ZCU102 Aurora 64b66b Design Example: RX/TX from quad 128, reference clock from quad 129

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@venkata

- Sorry to miss your question.

- I got no critical warning when I change refclk location contrains.

- However, it just like you specify refclk from quad129 but inside clock wizard RTL code, you are still using refclk from quad128. RTL code need to be modifed to reference to quad129 in order to work.

Andrew


Andrew
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Moderator
Moderator
1,901 Views
Registered: ‎02-16-2010

Re: ZCU102 Aurora 64b66b Design Example: RX/TX from quad 128, reference clock from quad 129

Jump to solution
RTL code is not required to be modified. Have you done the following check after updating REFCLK constraint to point to quad 129?

1. open implemented design
2. Search for IBUFDS_GTE4 in the design
3. create a schematic for the IBUFDS_GTE4 instance which connects to Aurora IP
4. Check the connectivity of inputs and outputs of this IBUFDS_GTE4 primitive
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------