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Registered: ‎01-13-2020

ZCU102 GEM3 external FIFO mode : receive bit errors

Hello All

I am using a ZCU102 board with the GEM3 - external FIFO for receiving Ethernet frames, and store these in BRAM, for later processing.

Vivado:2019.2
IP:ZYNQ with GEM3 enabled

When i receive data, there is bit errors in the received data. From the ILA i can see, the data is already erroneous when provided by the FIFO.

I can sniff in the network that the packet should be
0000 : ff ff ff ff ff ff dc a6 32 6d 87 51 80 80 77 77
0010 : 77 66 77 77 77 66 77 77 77 66 77 77 77 66 77 77
0020 : 77 66 77 77 77 66 77 77 77 66 77 77 77 66 77 77
0030 : 77 66 77 77 77 66 77 77 77 66 77 77 77 66 55 55

which is OK, it is a test packet.

From the logic trace it seems that there is a bit shift or a wrong sampling window ?

The GEM is configured as:

puts "enable GEM TX + RX"
write_verbose 0xFF0E0000 0x0000001C
puts "set FIFO bus width"
write_verbose 0xFF0E0004 0x048C0413
puts "enable FIFO interface"
write_verbose 0xFF0E004C 0x00000001
puts "set clocks"
write_verbose 0xFF180308 0x00000000

I am sending the data via a RPI-4 , it is the same if I use a point to point or with a switch in the middle. If i use a switch I can sniff with wireshark to be sure the data is correct on the wires.

Since the data is received 'almost' correct, I am assuming a configuration error. Are there more registers to set ?
The GEM3 is configured in the block design to use IOPLL @ 125 MHz , that is actually the default. Is this to fast/slow ?
Is the clock on the ZCU 102  good enough for gigabit ethernet reception ?

 

thanks 

 

Kris Provoost

rx_biterrors_ila.PNG
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Registered: ‎01-13-2020

Hello

I have been changing some settings in the PHY, and it appears that the data is now received correct. This actually means that the ZCU102 cannot be used out of the box with GEM 3 in external FIFO mode.

So I am not 100 % sure if this is the final fix. But at least it provides an error free reception each time.

The changes I had to make, are done via the MDIO interface by means of register accesses, as follows :

puts "WR extended register 0x0031"
write_verbose 0xff0e0034 0x5636001F
write_verbose 0xff0e0034 0x563A0031
write_verbose 0xff0e0034 0x5636401F
write_verbose 0xff0e0034 0x563A0000
puts "--"

puts "WR extended register 0x0032"
write_verbose 0xff0e0034 0x5636001F
write_verbose 0xff0e0034 0x563A0032
write_verbose 0xff0e0034 0x5636401F
write_verbose 0xff0e0034 0x563A00d3
puts "--"

 

The TX and RX are only enabled after the MDIO is setup.

 

gr.

Kris Provoost