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Observer
Observer
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Registered: ‎03-19-2020

ZCU102 multi-port xxv ethernet: XXV MAC block lock issue

Hi,

I have a ZCU102 and I want to configure two 10G/25G Ethernet Subsystem. 

But I run into problem like this : 

https://forums.xilinx.com/t5/Ethernet/ZCU102-Read-Register-in-10G-25G-Ethernet-Subsystem-IP-doesn-t/m-p/991852#M16234

That solution not for me. I was increase Range in Address Editor to 64K, Address with boundary 0x1_0000 with 0x00A0000000 and 0x00A0030000 is DMA address, 0x00A0010000 and 0x00A0020000 is xxv ethernet address. But, it's not solution for me. I get some log in linux:

xxv_block_lock.png

 

If I disable xxv_ethernet_1 in devicetree. xxv_ethernet_0 work well. But If i disable xxv_ethernet_0, both port don't work.

Anyone have any suggest for me, thanks very much.

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8 Replies
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Moderator
Moderator
514 Views
Registered: ‎08-25-2009

Hi @kv_dich ,

The most likely reason is the reference clock is not stable before the core is out of reset.

Is xxv_0 shared the reference clock for xxv_1?

"Don't forget to reply, kudo and accept as solution."
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Highlighted
Observer
Observer
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Registered: ‎03-19-2020

Hi nanz,

xxv ethernet configured in vivado with number GTH core is 2. If i configure with one core, it worked, even when i configure with 2 GTH and disable second xxv_ethernet_1 in device tree,  other worked. This issue in my case only happen when i enable both xxv_ethernet on device tree.

When I configure xxv_ethernet with one core and using SFP1 with lane1 X1Y13 (X1Y12 - SFP0, X1Y13 - SFP1, ...), Block lock issue is happen too.

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Moderator
Moderator
460 Views
Registered: ‎08-25-2009

Hi @kv_dich ,

Which version of the tool are you using?

"Don't forget to reply, kudo and accept as solution."
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Highlighted
Observer
Observer
457 Views
Registered: ‎03-19-2020

Hi nanz,

I'm using Vivado 2019.1. Linux kernel verison v2020.1 with bought license 10G/25G Ethernet Subsystem.

If you have any sample project which run two Ten Gigabits Ethernet on ZCU102 ? Please give it to me.

Thanks,

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Moderator
Moderator
422 Views
Registered: ‎08-25-2009

Hi @kv_dich ,

If you are using multiple cores in xxv IP, the DTS for clocks and interrupts of the xxv IP are generated incorrectly.

This issue is fixed in 2020.2. We have since provide 2019.2 patch which I have attached here for your reference.

 

"Don't forget to reply, kudo and accept as solution."
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Observer
Observer
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Registered: ‎03-19-2020

Hi @nanz 

Thank for your reply, I'm using Vivado 2019.1. Can you tell me how to using your patch?

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Moderator
Moderator
384 Views
Registered: ‎08-25-2009

Hi @kv_dich ,

We do not have 2019.1 patch. You can refer to the changes and make changes in 2019.1 as required.

"Don't forget to reply, kudo and accept as solution."
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Highlighted
Observer
Observer
348 Views
Registered: ‎03-19-2020

Hi @nanz 

I see that your patch only for devicetree generation, but I'm not using device tree which generated by SDK, it's make manual by myself.

My devicetree:

/*
 * CAUTION: This file is automatically generated by Xilinx.
 * Version:  
 * Today is: Sat Jun 15 02:28:07 2019
 */


/ {
	amba_pl: amba_pl@0 {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		ranges ;
		
		axi_dma_0: dma@a0001000 {
			#dma-cells = <1>;
			clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
			clocks = <&zynqmp_clk 71>, <&zynqmp_clk 72>, <&zynqmp_clk 72>, <&zynqmp_clk 72>;
			compatible = "xlnx,eth-dma";
			interrupt-names = "mm2s_introut", "s2mm_introut";
			interrupt-parent = <&gic>;
			interrupts = <0 89 4 0 90 4>;
			reg = <0x0 0xa0001000 0x0 0x1000>;
			xlnx,include-dre ;
		};
		
		axi_dma_1: dma@a0030000 {
			#dma-cells = <1>;
			clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
			clocks = <&zynqmp_clk 71>, <&zynqmp_clk 72>, <&zynqmp_clk 72>, <&zynqmp_clk 72>;
			compatible = "xlnx,eth-dma";
			interrupt-names = "mm2s_introut", "s2mm_introut";
			interrupt-parent = <&gic>;
			interrupts = <0 91 4 0 92 4>;
			reg = <0x0 0xa0030000 0x0 0x1000>;
			xlnx,include-dre ;
		};
		
		misc_clk_0: misc_clk_0 {
			#clock-cells = <0>;
			clock-frequency = <156250000>;
			compatible = "fixed-clock";
		};
		misc_clk_1: misc_clk_1 {
			#clock-cells = <0>;
			clock-frequency = <100000000>;
			compatible = "fixed-clock";
		};
		
		xxv_ethernet_0: ethernet@a0000000 {
			status = "okay";
			axistream-connected = <&axi_dma_0>;
			axistream-control-connected = <&axi_dma_0>;
			clock-frequency = <100000000>;
			clock-names = "rx_core_clk_0", "rx_core_clk_1", "dclk", "s_axi_aclk_0", "s_axi_aclk_1";
			clocks = <&misc_clk_0>, <&misc_clk_0>, <&misc_clk_1>, <&zynqmp_clk 71>, <&zynqmp_clk 71>;
			compatible = "xlnx,xxv-ethernet-3.0", "xlnx,xxv-ethernet-1.0";
			device_type = "network";
			local-mac-address = [00 0a 35 00 01 02];
			phy-mode = "base-r";
			reg = <0x0 0xa0000000 0x0 0x1000>;
			xlnx = <0x0>;
			xlnx,add-gt-cntrl-sts-ports = <0x0>;
			xlnx,anlt-clk-in-mhz = <0x64>;
			xlnx,axis-tdata-width = <0x40>;
			xlnx,axis-tkeep-width = <0x7>;
			xlnx,base-r-kr = "BASE-R";
			xlnx,clocking = "Asynchronous";
			xlnx,core = "Ethernet MAC+PCS/PMA 64-bit";
			xlnx,data-path-interface = "AXI Stream";
			xlnx,enable-datapath-parity = <0x0>;
			xlnx,enable-pipeline-reg = <0x0>;
			xlnx,enable-preemption = <0x0>;
			xlnx,enable-preemption-fifo = <0x0>;
			xlnx,enable-rx-flow-control-logic = <0x0>;
			xlnx,enable-time-stamping = <0x0>;
			xlnx,enable-tx-flow-control-logic = <0x0>;
			xlnx,enable-vlane-adjust-mode = <0x0>;
			xlnx,family-chk = "zynquplus";
			xlnx,fast-sim-mode = <0x0>;
			xlnx,gt-diffctrl-width = <0x4>;
			xlnx,gt-drp-clk = "100.00";
			xlnx,gt-group-select = "Quad X0Y0";
			xlnx,gt-location = <0x1>;
			xlnx,gt-ref-clk-freq = "156.25";
			xlnx,gt-type = "GTH";
			xlnx,include-auto-neg-lt-logic = "None";
			xlnx,include-axi4-interface = <0x1>;
			xlnx,include-dre ;
			xlnx,include-fec-logic = <0x0>;
			xlnx,include-hybrid-cmac-rsfec-logic = <0x0>;
			xlnx,include-rsfec-logic = <0x0>;
			xlnx,include-shared-logic = <0x1>;
			xlnx,include-statistics-counters = <0x1>;
			xlnx,include-user-fifo = <0x1>;
			xlnx,ins-loss-nyq = <0xa>;
			xlnx,lane1-gt-loc = "X1Y12";
			xlnx,lane2-gt-loc = "NA";
			xlnx,lane3-gt-loc = "NA";
			xlnx,lane4-gt-loc = "NA";
			xlnx,line-rate = <0xa>;
			xlnx,mii-ctrl-width = <0x4>;
			xlnx,mii-data-width = <0x20>;
			xlnx,num-of-cores = <0x1>;
			xlnx,ptp-clocking-mode = <0x0>;
			xlnx,ptp-operation-mode = <0x2>;
			xlnx,runtime-switch = <0x0>;
			xlnx,rx-eq-mode = "AUTO";
			xlnx,rxmem = <0x40000>;
			xlnx,statistics-regs-type = <0x0>;
			xlnx,switch-1-10-25g = <0x0>;
			xlnx,tx-latency-adjust = <0x0>;
			xlnx,tx-total-bytes-width = <0x4>;
			xlnx,xgmii-interface = <0x1>;
			
			xxv_ethernet_0_mdio: mdio {
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};
		
		xxv_ethernet_1: ethernet@a0020000 {
			status = "okay";
			axistream-connected = <&axi_dma_1>;
			axistream-control-connected = <&axi_dma_1>;
			clock-frequency = <100000000>;
			clock-names = "rx_core_clk_0", "rx_core_clk_1", "dclk", "s_axi_aclk_0", "s_axi_aclk_1";
			clocks = <&misc_clk_0>, <&misc_clk_0>, <&misc_clk_1>, <&zynqmp_clk 71>, <&zynqmp_clk 71>;
			compatible = "xlnx,xxv-ethernet-3.0", "xlnx,xxv-ethernet-1.0";
			device_type = "network";
			local-mac-address = [00 0a 35 00 01 03];
			phy-mode = "base-r";
			reg = <0x0 0xa0020000 0x0 0xFFFF>;
			xlnx = <0x0>;
			xlnx,add-gt-cntrl-sts-ports = <0x0>;
			xlnx,anlt-clk-in-mhz = <0x64>;
			xlnx,axis-tdata-width = <0x40>;
			xlnx,axis-tkeep-width = <0x7>;
			xlnx,base-r-kr = "BASE-R";
			xlnx,clocking = "Asynchronous";
			xlnx,core = "Ethernet MAC+PCS/PMA 64-bit";
			xlnx,data-path-interface = "AXI Stream";
			xlnx,enable-datapath-parity = <0x0>;
			xlnx,enable-pipeline-reg = <0x0>;
			xlnx,enable-preemption = <0x0>;
			xlnx,enable-preemption-fifo = <0x0>;
			xlnx,enable-rx-flow-control-logic = <0x0>;
			xlnx,enable-time-stamping = <0x0>;
			xlnx,enable-tx-flow-control-logic = <0x0>;
			xlnx,enable-vlane-adjust-mode = <0x0>;
			xlnx,family-chk = "zynquplus";
			xlnx,fast-sim-mode = <0x0>;
			xlnx,gt-diffctrl-width = <0x4>;
			xlnx,gt-drp-clk = "100.00";
			xlnx,gt-group-select = "Quad X0Y0";
			xlnx,gt-location = <0x1>;
			xlnx,gt-ref-clk-freq = "156.25";
			xlnx,gt-type = "GTH";
			xlnx,include-auto-neg-lt-logic = "None";
			xlnx,include-axi4-interface = <0x1>;
			xlnx,include-dre ;
			xlnx,include-fec-logic = <0x0>;
			xlnx,include-hybrid-cmac-rsfec-logic = <0x0>;
			xlnx,include-rsfec-logic = <0x0>;
			xlnx,include-shared-logic = <0x1>;
			xlnx,include-statistics-counters = <0x1>;
			xlnx,include-user-fifo = <0x1>;
			xlnx,ins-loss-nyq = <0xa>;
			xlnx,lane1-gt-loc = "X1Y12";
			xlnx,lane2-gt-loc = "NA";
			xlnx,lane3-gt-loc = "NA";
			xlnx,lane4-gt-loc = "NA";
			xlnx,line-rate = <0xa>;
			xlnx,mii-ctrl-width = <0x4>;
			xlnx,mii-data-width = <0x20>;
			xlnx,num-of-cores = <0x1>;
			xlnx,ptp-clocking-mode = <0x0>;
			xlnx,ptp-operation-mode = <0x2>;
			xlnx,runtime-switch = <0x0>;
			xlnx,rx-eq-mode = "AUTO";
			xlnx,rxmem = <0x40000>;
			xlnx,statistics-regs-type = <0x0>;
			xlnx,switch-1-10-25g = <0x0>;
			xlnx,tx-latency-adjust = <0x0>;
			xlnx,tx-total-bytes-width = <0x4>;
			xlnx,xgmii-interface = <0x1>;
			
			xxv_ethernet_1_mdio: mdio {
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};
	};
};
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