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siddadd
Visitor
Visitor
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Registered: ‎02-03-2020

ZU21DR: Timing errors in 40G Ethernet Core

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Hi,

I am using a 40G Ethernet core in the ZU21DR FPGA and I am getting a lot of timing errors internal to the ethernet core. 

For example,

AB
NamePath 1
Slack-0.658ns
Source<>/i_l_ethernet_0_pkt_gen_mon_0/rx_total_bytes_int_reg[16]/C   (rising edge-triggered cell FDSE clocked by rxoutclk_out[0]  {rise@0.000ns fall@1.600ns period=3.200ns})
Destination<>/i_l_ethernet_0_pkt_gen_mon_0/i_l_ethernet_0_rx_total_bytes_syncer/meta_reg[16]/D   (rising edge-triggered cell FDRE clocked by clk_out3_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
Path Groupclk_out3_clk_wiz_0
Path TypeSetup (Max at Slow Process Corner)
Requirement0.400ns (clk_out3_clk_wiz_0 rise@10.000ns - rxoutclk_out[0] rise@9.600ns)
Data Path Delay1.657ns (logic 0.076ns (4.587%)  route 1.581ns (95.413%))
Logic Levels0  
Clock Path Skew0.711ns
Clock Uncertainty0.137ns
Clock Net Delay (Source)2.971ns (routing 1.540ns, distribution 1.431ns)
Clock Net Delay (Destination)2.111ns (routing 1.412ns, distribution 0.699ns)
Clock Domain CrossingInter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.

 

AB
NamePath 663
Slack-3.535ns
Source<>/DUT/inst/i_l_ethernet_0_top_0/i_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1024_1518_bytes_accumulator/statsout_reg[28]/C   (rising edge-triggered cell FDRE clocked by rxoutclk_out[0]  {rise@0.000ns fall@1.600ns period=3.200ns})
Destination<>/DUT/inst/i_l_ethernet_0_top_0/i_axi_if_top/i_pif_registers/IP2Bus_Data_reg[28]/D   (rising edge-triggered cell FDRE clocked by clk_out2_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
Path Groupclk_out2_clk_wiz_0
Path TypeSetup (Max at Slow Process Corner)
Requirement0.400ns (clk_out2_clk_wiz_0 rise@10.000ns - rxoutclk_out[0] rise@9.600ns)
Data Path Delay4.984ns (logic 0.872ns (17.496%)  route 4.112ns (82.504%))
Logic Levels6  (LUT4=1 LUT5=2 LUT6=3)
Clock Path Skew1.161ns
Clock Uncertainty0.137ns
Clock Net Delay (Source)2.994ns (routing 1.540ns, distribution 1.454ns)
Clock Net Delay (Destination)2.581ns (routing 1.613ns, distribution 0.968ns)
Clock Domain CrossingInter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.

 

Can somebody suggest how to resolve these timing errors?

Thanks,

Siddharth

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1 Solution

Accepted Solutions
nanz
Moderator
Moderator
417 Views
Registered: ‎08-25-2009

Hi @siddadd ,

Are these timing errors in the example design? If you have not tried, can you please first try the example design first and see if you still see it? 

If so, please upload your xci file here. 


-------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

-------------------------------------------------------------------------------------------

View solution in original post

2 Replies
nanz
Moderator
Moderator
418 Views
Registered: ‎08-25-2009

Hi @siddadd ,

Are these timing errors in the example design? If you have not tried, can you please first try the example design first and see if you still see it? 

If so, please upload your xci file here. 


-------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

-------------------------------------------------------------------------------------------

View solution in original post

siddadd
Visitor
Visitor
386 Views
Registered: ‎02-03-2020

Hi @nanz ,

I tried the example design and did not get any timing errors. I noticed that some constraints were optimizing parts of the ethernet core which may have been causing the issue. I am re-running with updated constraints to see if the timing errors are resolved.

Thanks,

Siddharth