12-07-2018 01:33 AM
I am planing to use ZU5-B900 (-1 Speed grade) MPSoC device.
I am short of IO and hence I am planning to use SGMII over LVDS from PL IO's.
Does MPSoC device support this? Please let me know if it has been validated in some dev-boards.
12-10-2018 06:34 AM
I had the same question and so worked out the answer from the documentation. As you're short on I/Os, I'll assume that you will be using Asynchronous SGMII over LVDS.
My understanding is that the answer is YES, all of the Zynq Ultrascale+ devices (and all available speed grades) support SGMII over LVDS at 1.25Gbps.
The product guide for the 1G/2.5G Ethernet PCS/PMA or SGMII core states: "Asynchronous SGMII/1000BASE-X over LVDS is supported in UltraScale and UltraScale+ devices only". Not very specific, I know, so I dug a bit deeper to find out which (if any) Ultrascale or Ultrascale+ devices/speed grades did NOT support it.
As described in the product guide, in Ultrascale and Ultrascale+ devices, the SGMII over LVDS interface is implemented with High Speed SelectIO resources in Native Mode. How this works is described in the Native High-Speed I/O Interfaces guide (XAPP1274) but the important point to note is that it uses DDRs - ie. the sampling clock is half the frequency of the incoming data rate, and it samples on both rising and falling transitions. Knowing this we can check the Zynq Ultrascale+ datasheet for the maximum data rate of the LVDS DDR RX/TX interfaces. We find that it is 1.25Gbps for all speed grades.
In my experience, the best way to know if something is going to work is to run it through the Vivado tools. The tools usually have all of the timing information of the device you want to use and will flag any timing issues when you try to do something that the device is not capable of doing. I've done that for myself using a -1 speed grade device and I get the all clear.
As for verification, I don't know of any ZUS+ boards that use SGMII over LVDS but I'm currently working on one and I'll post back our results in the following weeks.
12-10-2018 09:32 PM
Thanks for the elaborate info.
I have done a similar trials on vivado and seems to have no issues with the CORE. I would want to know more about such implementation, if some one has tried on a few specific SGMII PHY. Would like to understand more If there are any sort of issues observed or workaround or may be someone who could share more insights on the implementation details on hardware perspective would be really appreciated.