Zynq-7000 RGMII interface

[frankwestgeest]

According to UG585 chapter 16 the Zynq-7000 devices (we are using the XA7Z020) support a RGMII interface for connection to an external Ethernet PHY. RGMII v2.0 is supported. In RGMII v2.0 Delay on Destination (DoD) and Delay on Source (DoS) are specified. For DoD at the receiver the clock signal is delayed internally. For DoS at the transmitter the clock signal is generated with a delay.
Does Xilinx support both these features? How can they be enabled?

Best regards,
Frank Westgeest

[pvenugo · Accepted solution]

Hi @frankwestgeest ,

In Zynq PS GEM,  user can not add clock skew to the TX or Rx clock, therefore the skew must be added by the PHY or the PCB trace.

If you are using the and external FMC it is very unlikely that the Zynq MIO pins are routed to the FMC connector, but when routed through EMIO it can be included in PL section. In the case of GMII-to-RGMII IP usage this core has an option to add 2ns of skew to the TX clock wheras RX clock skew is no available and has to be added by PHY using baremetal application or linux device tree.

Regards

Praveen