04-08-2021 07:11 PM - edited 04-09-2021 08:13 AM
I am trying to build the FSBL for a custom Zynq 7000 (XC7Z030) board. When I boot with U-boot the ethernet works fine in my app.elf. I have compared the ps7_init files from the U-boot source and they look very similar. I have attached the ps7_init included in my Vitis FSBL project.
When I power the target, it boots my kernel just fine, but the PHY acts as if it is never initialized (one of the LEDs turns off that usually stays on). Inspecting the gem0 registers, I see a lot of receive alignment errors and I cannot sniff any packets from the target in Wireshark. Other than that, the configuration looks identical to when booted with U-boot. I'm assuming one of the clocks is not getting initialized properly or something.
Again, when I boot with U-boot everything works as expected. What is going on with the FSBL?
04-15-2021 03:01 AM
Hi @JustBenj ,
Are you using Petalinux in Vitis? Have you tried petalinux flow? Can you please share your bootlog and DTS file?
I assume you are using RGMII MIO with Zynq PS GEM?