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Registered: ‎04-08-2021

Zynq Ethernet not working with FSBL

I am trying to build the FSBL for a custom Zynq 7000 (XC7Z030) board. When I boot with U-boot the ethernet works fine in my app.elf. I have compared the ps7_init files from the U-boot source and they look very similar. I have attached the ps7_init included in my Vitis FSBL project.

  1. Using Vivado 2020.2 I configured my PS block and exported the XSA.
  2. Using Vitis 2020.2 I created a Zynq FSBL application project based on the XSA.
  3. Built the FSBL and created BOOT.bin

When I power the target, it boots my kernel just fine, but the PHY acts as if it is never initialized (one of the LEDs turns off that usually stays on). Inspecting the gem0 registers, I see a lot of receive alignment errors and I cannot sniff any packets from the target in Wireshark. Other than that, the configuration looks identical to when booted with U-boot. I'm assuming one of the clocks is not getting initialized properly or something.

Again, when I boot with U-boot everything works as expected. What is going on with the FSBL?


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Registered: ‎08-25-2009

Hi @JustBenj ,

Are you using Petalinux in Vitis? Have you tried petalinux flow? Can you please share your bootlog and DTS file? 

I assume you are using RGMII MIO with Zynq PS GEM? 


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If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

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