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Xil_printf
Visitor
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Registered: ‎02-25-2021

Zynq Ultrascale+ Bare Metal Ethernet Driver - SGMII

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Did anyone use the bare metal driver with SGMII? I have a custom board with the TI DP83867ISRGZR.

What do I need to change in the bare metal driver code to make it work with SGMII interface?

Is there a development board that uses ultrascale+ and SGMII? We are using Zynq UltraScale+ MPSoC ZU15EG device. All the Ultrascale+ boards I see use RGMII.

On the vivado side, I turned on GT Lane1 on GEM1, see screenshot below. 

Anyone who used the SGMII interface please let me know. Thanks in advance.

GEM config.PNG
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nanz
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Registered: ‎08-25-2009

Hi @Xil_printf ,

I am not sure if you've found a solution to your issue. But here is a summary of how to enable PS-GTR SGMII on a customer board:

  1. Enable SGMII in MAC here by adding the mentioned lines:

https://github.com/Xilinx/embeddedsw/blob/master/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/netif/xemacpsif_hw.c#L84

XEmacPs_SetOptions(xemacpsp, XEMACPS_SGMII_ENABLE_OPTION);

/* pcs control autoneg enable */

XEmacPs_WriteReg(xemacpsp->Config.BaseAddress, 0x200, XEmacPs_ReadReg(xemacpsp->Config.BaseAddress, 0x200) | 0x9000);

 

  1. Add code to initialize your phy here:

https://github.com/Xilinx/embeddedsw/blob/master/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/netif/xemacpsif_physpeed.c#L691

If your SGMII phy make is Marvell or TI, those existing functions (for RGMII) can be used as a reference and the necessary SGMII config registers should be added.


-------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

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nanz
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Registered: ‎08-25-2009

Hi @Xil_printf ,

SGMII support has been added to emacps driver if this is what you are asking. 

Please check the source codes: 

https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/emacps/src/xemacps.h

and the option - XEMACPS_SGMII_ENABLE_OPTION.


-------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

-------------------------------------------------------------------------------------------
Xil_printf
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Registered: ‎02-25-2021

@nanz Thanks for the reply. I did enable that option. Is there anything else I need to change?  I'm using a 125MHz external ref clock.  I notice the dev boards such as zcu 102 uses a 25MHz clock. Do I need to modify anything for that? I'm testing the code in Loopback mode as is. Currently my code just sits at this line " while (!FramesTx); "

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kjstephen
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Registered: ‎05-23-2017

Hi,

I apologize if this sounds like "well, did you turn on the power?" but it's true that there are several hardware configurations that you have to get right for this to work.

(I just spent 2 weeks trying to get this interface to work using a Marvell PHY, possibly the TI PHY also has as many tricky things that you have to get right.)

Besides your screenshot above, there is another page in the Zynq Wizard for Clock Configuration. Under "GT Lane Reference Frequency" make sure you have your external reference clock set correctly. For example, I used the RefClk0 input for all 4 GEMs. Make sure you have it set for your configuration. Also, under the Output Clocks tab, under "Low Power Domain>Peripherals" there is another setting for the GEMs internal clock. This gets set by default but make sure it is 125MHz.

kjstephen_0-1615531350192.png

If you are using the internal (local) loopback, I don't think it works in SGMII mode. Try using RGMII only. (I never tried this loopback at all, I was focused on getting the connection to the PHY working) You will have to manually set the GEM registers to do this because the defaults were set by the Zynq Wizard.

Now, the trickiest part. Have you configured the PHY correctly? The example design for the XemacsPs sets up the PHY assuming it is an RGMII interface. Read the PHY data sheet carefully and figure out what you have to do to make it SGMII, and modify the code accordingly. In my experience with the Marvell PHY, there were places where you have to "reset" after setting a configuration, then you have to wait some unknown time for the reset to happen before you can proceed. It took some experimenting to get that right.

The thing that finally made it work was really stupid: plug it in! Nothing happened until I connected the cable to the spare Ethernet port on my laptop. Then both the PHY and the GEM could do their auto-negotiation thing, the lights came on and packets started flowing.

 

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nanz
Moderator
Moderator
268 Views
Registered: ‎08-25-2009

Hi @Xil_printf ,

Have you had an update regarding the issue? GEM SGMII PS-GTR will use a 125MHz ref clock as the screenshot shown above.

You can set PCS_Control register to loopback the data if you like.


-------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

-------------------------------------------------------------------------------------------
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nanz
Moderator
Moderator
179 Views
Registered: ‎08-25-2009

Hi @Xil_printf ,

I am not sure if you've found a solution to your issue. But here is a summary of how to enable PS-GTR SGMII on a customer board:

  1. Enable SGMII in MAC here by adding the mentioned lines:

https://github.com/Xilinx/embeddedsw/blob/master/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/netif/xemacpsif_hw.c#L84

XEmacPs_SetOptions(xemacpsp, XEMACPS_SGMII_ENABLE_OPTION);

/* pcs control autoneg enable */

XEmacPs_WriteReg(xemacpsp->Config.BaseAddress, 0x200, XEmacPs_ReadReg(xemacpsp->Config.BaseAddress, 0x200) | 0x9000);

 

  1. Add code to initialize your phy here:

https://github.com/Xilinx/embeddedsw/blob/master/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/netif/xemacpsif_physpeed.c#L691

If your SGMII phy make is Marvell or TI, those existing functions (for RGMII) can be used as a reference and the necessary SGMII config registers should be added.


-------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

-------------------------------------------------------------------------------------------

View solution in original post

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