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tchin123
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Registered: ‎05-14-2017

Zynq Ultrascale+ Ethernet frame connection to both PL and PS block

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I'm connecting an Ethernet  to the Ultrascale+ FPGA and would like both the PS (Arm processor) and the PL to process the Ethernet frame. First time using both the PS and PL block

1) Does the Ethernet IP has one channel that interface to the ARM CPU and one channel that interface to the PL logic. Not sure how this is implemented

2) Is it better to have the Ethernet IP situated on the PL side then also pass the connection to the PS side or is it better to implement it in the PS side then pass the frame over to the PL logic.

3) To  use the PS (ARM) in an FPGA design, does one start with using the IP Integrator to incorporate the Zynq processor into a Block Design first then incorporate the Block Design into the FPGA VHDL design?

 

 

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nanz
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Registered: ‎08-25-2009

PS GEM is hardened, so no PL FPGA resources will be used.

To use PL MAC, the customer can check the source codes, have the access to DMA/FIFO etc…

On the driver side, PS GEM uses MACB and it supports shared MDIO and fixed link etc.. While PL MAC uses axi ethernet linux driver which does not have the support.

Here are the driver wiki pages for MACB and AXI Ethernet Linux driver:

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841740/Macb+Driver

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842485/Linux+AXI+Ethernet+driver

These are the reference designs that users can pick whichever suits their needs.

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/478937213/MPSoC+PS+and+PL+Ethernet+Example+Projects


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nanz
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Registered: ‎08-25-2009

Hi @tchin123 ,

There are a couple of options that I think you may consider. (I assume you are talking about 1G)

1) Using PS GEM with an external FIFO interface. This is normally used when Ethernet DMA is not required. So the ethernet frames will be routed to PL and you can add your own blocks to process the Ethernet data. 

2) Using PL Ethernet IP for your need (1G/2.5G AXI Ethernet IP). This way you will have the access to the user interface of the core. 

Here are examples of pl processor designs:

https://github.com/Xilinx-Wiki-Projects/ZCU102-Ethernet/tree/main/2019.2

 


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tchin123
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Registered: ‎05-14-2017

Does it make any sense for both the PS and PL process the Ethernet frame or normally only one or the other is possible?

What I'm thinking is that since the ethernet is connected to the network, I assume the PS is responsible to configure the MAC, IP address during power on. But once that is completed, I would like the PL to process the frame for performance

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nanz
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Registered: ‎08-25-2009

Hi @tchin123 ,

In most use cases it's exactly as what you described - the processor is used to program registers and bring MAC up and running. The ethernet frames processing (if required) can be left to user logics. 


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tchin123
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Registered: ‎05-14-2017

This is where I'm not sure how the interface between the PS and PL interact with each other. Does the IP has two interfaces. a frame interface for the PL processing and a different interface to bring the IP up? Secondly, in term of processing the ethernet frame, in a normal scenario in there only one processing unit, either the PS or the PL but not both?

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nanz
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Registered: ‎08-25-2009

Which IP core are you considering?

If you are using PS GEM, PS will have control over setting the GEM registers. If you enable external FIFO interface, you will see the interface exposed to users to PL; and you can add your own logic to process the data. 

If you are asking about1G AXI Ethernet, when the processor mode is enabled, there will be an AXI buffer included in the core which provides a AXI4 Lite interface so the processor has the access to registers. Then the AXIS interface (normally connected to AXI DMA/FIFO) are for packets processing. 

Yes, in the normal scenario, you will only need either PS or PL. 


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tchin123
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I'm using the AXI 1G Ethernet subsystem in the PL and frames are process directly from the m_axis_rx and s_axis_tx by the PL.

In this scenario, the PS has no control over the Ethernet frame, is this correct? In this case I guess it is not possible for PS to access the frame or am mistaken. Can the PS perform any background activity and share the frames bus with the PL?

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nanz
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Registered: ‎08-25-2009

Hi @tchin123 ,

This is correct. PS will have no control over your Ethernet frames. 

But if you connect your AXI4 Lite interface with the processor, it will have the control over the registers of the Ethernet IP to be able to configure it. 


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tchin123
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OK, if the  AXI 1G Ethernet subsystem is use for the PL to process the frame then what purpose is it to enable the AXI buffer from the Vivado Wizard. I thought this is a feature to allow the frame to be buffered before the PS can process it.

If the PS wants to access the frame then isn't it better to use the GEM in the PS section instead of using the PL AXI 1G ethernet and enabling the AXI buffer?

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nanz
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Registered: ‎08-25-2009

Hi @tchin123 , 

This feature is to provide a processor interface so the processor is able to configure/init the IP's registers and bring it up and running. 

Yes, GEM will be a better option if you'd like to use PS to process the frame so that you can save on PL resources. 


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tchin123
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OK, when using the AXI 1G ethernet, enabling the IP Wizard MAC feature provides IP register configuration, is this via the axi_lite bus or the frame bus?

I notice that this feature allow the user to define the TX/RX memory size also. Is this for buffering the ethernet frame because I thought the PS has no control or access to the frame if the IP is solely control by the PL.

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nanz
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Registered: ‎08-25-2009

Hi @tchin123 ,

It's the AXI Lite interface.

I believe you mean the AXI Ethernet buffer memory size? This is to support features such as TX and RX TCP/UDP Partial Checksum offload, IPv4 TX and RX TCP/UDP full checksum offload, TX and RX VLAN stripping, tagging and Extended filtering for multicast frames are provided using this infrastructure core. You can refer to PG138 for more details. 


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tchin123
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Yes the PG138 was helpful but sometime detail are not fully explain which introduce question. Since the IP{ Wizard, AXI Ethernet buffer memory size is use to support all the features that was mentioned then aren't the PS is processing the frame? I thought the frame is only process in the PL.

This is where it is confusing, how can both PL and PS process the ethernet frame 

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nanz
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Registered: ‎08-25-2009

Hi @tchin123 ,

Are you using any of the software stacks or drivers? This is normally considered to choose between a processer system and without. Together with AXI DMA, it can do checksum offload, tagging etc.  You do not need to use the supported feature of the Ethernet buffer if not required. 


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tchin123
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If sw stack and driver is used then this is where the supported feature of the Ethernet TX/RX buffer is required when using the 1G AXI subsystem?

If this is correct, then I believed it is best just to use the GEM in the PS instead,  then why use the 1G AXI subsystem in the PL and turning on the buffer feature. I'm just trying to understand the different way of implementation.

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nanz
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Registered: ‎08-25-2009

PS GEM is hardened, so no PL FPGA resources will be used.

To use PL MAC, the customer can check the source codes, have the access to DMA/FIFO etc…

On the driver side, PS GEM uses MACB and it supports shared MDIO and fixed link etc.. While PL MAC uses axi ethernet linux driver which does not have the support.

Here are the driver wiki pages for MACB and AXI Ethernet Linux driver:

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841740/Macb+Driver

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842485/Linux+AXI+Ethernet+driver

These are the reference designs that users can pick whichever suits their needs.

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/478937213/MPSoC+PS+and+PL+Ethernet+Example+Projects


-------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

-------------------------------------------------------------------------------------------

View solution in original post

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