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mrwanghl
Participant
Participant
3,953 Views
Registered: ‎04-01-2012

aurora v5.2 can't work stabllity in vertix5

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                 problem description: when use aurora v3.0 in virtex the channelup is still high and it seems to work stability, but we change aurora v3.0 to be aurora v5,2 (ISE 13.2) ,the channelup can't always be high, the main difference between the aurora v3.0 and aurora v5.2 is the DLL and PLL, aurora v5.2 use PLL , is PLL strictly demands the accuracy of the reference oscillator ? I wish to the answer....  

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ckarman
Xilinx Employee
Xilinx Employee
4,307 Views
Registered: ‎06-01-2011

Hi mrwang,

 

I assume you're using Aurora 8b10b here. Did you use example design's CC module? If so, there's an issue with the clock correction module of aurora 8b10b v5.2 core that might explain why your channelup won't stay high in your situation.

Please refer to AR 38956 (http://www.xilinx.com/support/answers/38956.htm) and make sure you made the necessary change for this core, if you're using this module.

 

If you have your own CC module, then please make sure you follow the requirement on asserting DO_CC as stated in UG page 89 (http://www.xilinx.com/support/documentation/ip_documentation/aurora_8b10b_ug353.pdf)

Also check your refclk ppm difference and make sure it's within +- 100 ppm as stated in the spec page 36 (http://www.xilinx.com/support/documentation/ip_documentation/aurora_8b10b_protocol_spec_sp002.pdf)

 

 

Thanks,
Chris

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rcingham
Teacher
Teacher
3,943 Views
Registered: ‎09-09-2010
We have no problems with Aurora v5.2-based links here. The reference clock is from a synthesizer fed from a +/-50ppm crystal.

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"If it don't work in simulation, it won't work on the board."
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ckarman
Xilinx Employee
Xilinx Employee
4,308 Views
Registered: ‎06-01-2011

Hi mrwang,

 

I assume you're using Aurora 8b10b here. Did you use example design's CC module? If so, there's an issue with the clock correction module of aurora 8b10b v5.2 core that might explain why your channelup won't stay high in your situation.

Please refer to AR 38956 (http://www.xilinx.com/support/answers/38956.htm) and make sure you made the necessary change for this core, if you're using this module.

 

If you have your own CC module, then please make sure you follow the requirement on asserting DO_CC as stated in UG page 89 (http://www.xilinx.com/support/documentation/ip_documentation/aurora_8b10b_ug353.pdf)

Also check your refclk ppm difference and make sure it's within +- 100 ppm as stated in the spec page 36 (http://www.xilinx.com/support/documentation/ip_documentation/aurora_8b10b_protocol_spec_sp002.pdf)

 

 

Thanks,
Chris

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