07-31-2012 10:30 AM
2 virtex5 boards are connected via aurora v5_2 duplex 8B10B - 2 GTP tiles = 4 channels streaming duplex topology, 1 REF_CLK pin = 156,25 MHz, line rate 3,125 Gbit, using 20cm 6,25Gbit cable.
HARD_ERROR occurs occasionaly, only on 1 and always the same channel, in groups of rx_buf_err occurances due to rx_buff underflow, followed by
rxnotintable 4 user_clk cycles later, and rxdsiperr 43 user_clk cycles later
V2 answer record 14920 offer to increase the nr of cc chars: "have the TX side of your design insert more clock correction characters" but this seems not to apply to tile macros infered by coregen.
should i make use of ug196 table 7-27 "Separate Reference Clocks, RX uses RXRECCLK" and connect RXRECCLK also as user_clk thus disabling clock correction?
08-01-2012 02:03 AM
Can you try with aurora_8b10b_v5_3 core?
CC characters are being transmitted from standard_cc_module and example design of aurora_8b10b_v5_2 core had a bug which prevents CC transmission. It got fixed in aurora_8b10b_v5_3 core.
08-03-2012 08:23 AM
as I just wrote Wendy Duffy,
v6.1 is used (didn't find any aurora_8b10b v5.3)
I also have prepared a design where cc_module is left unconnected, I'm testing it right now, it also shows the exact same behaviour.
thank you for your time,
08-10-2012 08:34 AM
invert the reset to the standard_cc_module. it's defined as "all lanes up"
lane_up_reduce_i <= AND_REDUCE(lane_up_i);
and acts as an active_high reset inside standard_cc_module, therefore when all lane are up, clock correction symbols (enabled by signal DO_CC) are NEVER GENERATED.
-- (this signal should actually now be called "one_or_more_lanes_are_down"!!!)
lane_up_reduce_i <= NOT(AND_REDUCE(lane_up_i));
when telling Erik Schidlack (Xilinx) about the cc_module reset scheme he couldn't believe..
thanx again Erik!