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yesuraju@408
Observer
Observer
1,092 Views
Registered: ‎11-21-2017

bank voltage conflicts

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Hai everyone

                       I am using kc705 evaluation board (xc7k325t fpga)  in that when i am configuring i am facing issues.

            output_enable_out----lvcmos15

            clk_p------lvds

            clk_n-----lvds

 

but these 3 pins are related to bank33 ,it will shows error like below.anyhow i am using master constraints located in kc705 user guide.,what i have to place in IOSTANDARD.

           ----------ERROR------------------------

Rule violation (BIVC-1) Bank IO standard Vcc - Conflicting Vcc voltages in bank 33. For example, the following two ports in this bank have conflicting VCCOs:
output_enable_out (LVCMOS15, requiring VCCO=1.500) and clk_p (LVDS, requiring VCCO=1.800)

 

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sandrao
Community Manager
Community Manager
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Registered: ‎08-08-2007

Looking at the KC705 UG810 Bank 33 is powered at 1.5V so the LVCMOS15 is correct. 

The Sysclk that is also on bank 33 has an external DIFF_TERM resistor see Figure 1-10, therefore you need to set the DIFF_TERM = FALSE for this IO pair. 

When DIFF_TERM = TRUE there is a dependency on the Vcco and it needs to be 1.8V for a HP bank. When DIFF_TERM = FALSE the Vcco can be 1.5V and the DIFF_TERM is external. 

Thanks,

Sandy


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sandrao
Community Manager
Community Manager
1,093 Views
Registered: ‎08-08-2007

Looking at the KC705 UG810 Bank 33 is powered at 1.5V so the LVCMOS15 is correct. 

The Sysclk that is also on bank 33 has an external DIFF_TERM resistor see Figure 1-10, therefore you need to set the DIFF_TERM = FALSE for this IO pair. 

When DIFF_TERM = TRUE there is a dependency on the Vcco and it needs to be 1.8V for a HP bank. When DIFF_TERM = FALSE the Vcco can be 1.5V and the DIFF_TERM is external. 

Thanks,

Sandy


------------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub , Versal Blogs and the Versal Useful Resources .

------------------------------------------------------------------------------------------------

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balcells
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Registered: ‎01-23-2018

Hi

I'm facing the same issue, when I try to use SYSCLK_P(_N) as input of a clk_wiz (generate by IP Catalog -> clocking -> clocking Wizard)

I'm using a KC705 board with KC705_Rev1_0_U1.ucf.xdc file where I tried to add set_property DIFF_TERM FALSE [get_ports SYSCLK_P] (same for _N)

but I always have the same issue at implementation:

 

[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 33. For example, the following two ports in this bank have conflicting VCCOs:
GPIO_SW_N (LVCMOS15, requiring VCCO=1.500) and SYSCLK_P (LVDS, requiring VCCO=1.800)

 

regards

André

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