cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
mistercoffee
Scholar
Scholar
7,397 Views
Registered: ‎04-04-2014

bug with 10GE example code

Hi,

 

I'm not sure where to report this. I was going to open a webcase but see I can't do that anymore. This seemed like the best place to put it.

 

In the 10GE core example code there is a bug in MAC_fifo_block.vhd. Lines 264-267 have the following code:

 

rx_axis_mac_aresetn_i => not reset or rx_axis_mac_aresetn;

tx_axis_mac_aresetn_i => not reset or tx_axis_mac_aresetn;

rx_axis_fifo_aresetn_i => not reset or rx_axis_fifo_aresetn;

tx_axis_fifo_aresetn_i => not reset or tx_axis_fifo_aresetn;

 

The or should be and. Otherwise the reset cannot be triggered by the aresetn alone as it is active low.

 

0 Kudos
1 Reply
yenigal
Xilinx Employee
Xilinx Employee
7,390 Views
Registered: ‎02-06-2013

Hi

 

Thanks for reporting this.

 

I will communicate this to the internal team and see that it gets fixed in the future version of the core.

 

 

Regards,

Satish

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------
0 Kudos