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Registered: ‎05-01-2019

cpri v8.9 external loopback

I am new to CPRI and GTX related designs, so please forgive any silly question I going to ask.

I am working on the CPRI example design, with a Kintex 7 FPGA.

I have one Cpri with core implemented inside driving clocks to 3 other Cpri's all of them configured in master mode. 

I am performing the following test –

1.insert optic loopback to the CPRI status code and alarm register (0x0)

3.value should be 0xf (link is up)

The issue that I see is that sometimes after system initiate one or two of the CPRI’s are reporting 0x11(Attempting L1 sync) value instead 0xf,

I want to understand why this happens maybe the reset sequence is wrong …..

Please advice

P.S. I have see that clocks driven from Cpri 1 locked before reset release of the other Cpri's 

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4 Replies
Xilinx Employee
Xilinx Employee
Registered: ‎08-02-2007 

What's the line rate you want to run for 4 CPRIs?

I'm still a bit confused about your system structure. All the CPRIs are master, what is connected at Slave side? Are 4 CPRI lanes related or totally independent to each other?

If you set all CPRI to internal loopback, does it work? For L1 sync status, it's master and slave trying to negotiate a line bit rate supported by both master and slave.

For 4 CPRI sharing clocks structure, you can take a look at Figure 4‐14 of CPRI PG056, and double check if connection is correct.


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Registered: ‎05-01-2019

Hi and Thanks for the reply,

The line rate that I use is 10Gbps.

every Cpri is tottaly independent to each other and In the interface of each SFP I insert optic loopback.

The qustion is :

If I have 2 Independent Cpri that receives the same clock and connected in a similiar way,

so how can I see after reset diffrent status from them ?

status of one is 0xf and status of the other is "attempting L1 sync"

It is possible to say that each Cpri generate its own Tx and due to the loopback sync on it in the Rx

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Xilinx Employee
Xilinx Employee
Registered: ‎08-02-2007


The best way is to evaluate the behavior after in simulation. You can do that by highlighting CPRI IP -> Right click -> open IP example design -> run simulation. Make sure you have added necessary GT signals.

Firstly please ensure the board jump is set correctly. If not, some SFP connectors might be disabled.

Normally you need to check the value of loopback input is set correctly :

Loopback (defaults to 00)

00: Normal Operation

10: Near-end physical medium attachment (PMA) Loopback

If you use external SFP cables, loopback value should be 00.

Before you attempt L1 sync, you need to ensure QPLL is locked, GTRESETDONE is asserted, and then TX phase alignment is completed (only when your device family is 7-series, or line rate is 8B10B for Ultrascale device family).

If the CPRI is in slave mode, you need to change core_is_master to 0, and ensure Slave Transmit Enable (bit 8 of

General Configuration and Transmit CPRI Alarms Register) is 1.

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Xilinx Employee
Xilinx Employee
Registered: ‎05-01-2013

Have you tried GT PMA near end loopback?

Still has the issue in the GT loopback mode?

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