01-24-2014 02:40 AM
i am trying to interface virtex 6 ML605 with PC through ethernet....basic data transfer(files) between them....i'm trying to implement it with TEMAC IP core but unable to succeed..so plz help me how to proceed with this..and i also wanted to implement this interface without a processor....
if anyone of you worked on this interface....can you plz share the procedure how to do
it is easier to implement it with ip cores or with processor?????
01-24-2014 07:05 AM
To use TEMAC with processor or not depends on your design requirement , but I think you can find enough example designs both the ways.
There is a detailed Example Design in UG800
Though the below link mentions V5, you can use similar concepts for V6, have loop back and check the packets in wireshark
Hope this helps
01-24-2014 03:56 PM
01-24-2014 09:15 PM
03-04-2014 09:54 PM
the pdf u have linked is for ethernet wrapper v2.3 but my xilinx version supports ethernet MAC wrapper v1.4.....i downloaded it and did the same....i am able to connect the fpga board with my PC....i.e i can see on wireshark that the device is connected but i am unable to send or receive data .....
while receiving data from PC it was showing error as IP check sum offload error in wireshark....so the data is not being received by FPGA although on the ethernet port it was showing that a transaction has happened (by blinking ).
while sending data...data that is being sent is not coming out of the MAC wrapper....i am sending a pattern 00110011.....but it is not showing any output.
the signals coming out from MAC wrapper are as below (as observed in chipscope):
EMACCLIENTTXSTATSVLD = 0
i hav a doubt ...is it that u hav to send a FRAMED 8-bit data to the input of wrapper....or any 8 bit data will do the work.