gtwizard (3.3) issue when choosing TX CLOCK SOURCE

[maxinquaye]

Hello,

in the 7 series FPGAs Transceiver Wizard (3.3) the GUI fails to display the quad setup when I choose REFCLK0 for TX CLOCK SOURCE. See the image in the appendix.

When I change back to REFCLK1 the quad setup reappears.

Furthermore, when I change the TX PLL or the gt row back and forth the TX CLOCK SOURCE is automatically set back to REFCLK1.

Related questions:

What exactly does the selection of TX CLOCK SOURCE do to the code?

Should it change the PLL?REFCLKSEL port in the common file? I checked these two ports for different selections in the IP example and they are always both set to "001"?

Is the manual edit of these ports the same as choosing TX CLOCK SOURCE?

Where else can I verify that the change of TX CLOCK SOURCE is really implemented?

Thanks

[venkata]

I believe you are using Artix-7 device.

This issue does not look to be reproducible on all platforms. I do not find the issue at my end with similar settings in the snapshot shown by you. Do you find the same issue on a different machine?

Which OS are you using?

[athandr]

Hi,

What exactly does the selection of TX CLOCK SOURCE do to the code?

A: Based on the TX CLOCK SOURCE, the output of the IBUFDS_GTE2 of a specific quad is routed to respective neighbouring quads or the same quad, based on this selection. Check the image below  

[smarell]

Looks like a GUI issue to me. There are no hardware/wizard limitations.

Here are some pointers-

1. Use a supported OS.
2. Try this on a different machine.
3. Re-install vivado.

[maxinquaye]

Thanks for the answers.

I use Gentoo but I could reproduce the error on a Windows machine. You need to enable more than one channel and then change TX CLOCK SOURCE.

I use Artix 7-device, yes.

Maybe someone could answer these questions:

Is the manual edit of the PLL?REFCLKSEL ports in the common file the same as choosing TX CLOCK SOURCE in the wizard?

Where can I verify that the change of TX CLOCK SOURCE is really implemented?

[venkata]

This looks to be OS dependant. I do not find the issue in Linux environment, but it shows up in Windows machine.

PLLREFCLKSEL need not be edited if the same clock is connected both the GTs. You can connect them together. Based on the REFCLK selection output from the corresponding IBUFDS buffer is connected to GTPE2_COMMON.

[tburgess]

I'm just now seeing something similar, except I'm only using 5 receivers Y32-35 and Y36, both

with QPLLs sharing the Q8 REFCLK .

Maybe if you experiment too much with the quad clock configuration the wizard gets confused

and loses the plot? (Win 7)

After messing around some more, I thought I had the quad display back, but after closing

and reopening the project/IP the quad display was still blank. Guess I'll start again from

scratch with no experiments and see what happens.