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Visitor
Visitor
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Registered: ‎12-19-2016

issues regarding implementation of aurora 8b/10b core in ml505

hi

 I am available with ml505 virtex5 fpga. i am trying to implement example design of aurora 8b/10b core with single lane . i am selecting GTPY3 TILE 0 which is having loopback and onboard 125 mhz clock. i routed lane up and channel up signal to leds. but it is not blinked. how i implemnt this example design. will you reply the steps?

 

is tre any board setting changes?

 

thank you

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Xilinx Employee
Xilinx Employee
625 Views
Registered: ‎11-20-2017

Hi 

 

please check the following

pin LOC constraints related to Refclk and init_clk

check the INIT_CLK source on board and frequency of INIT_CLK.

Are you doing the external loopback.?

please let me know what is the Tool Version you are using

 

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