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Observer
Observer
645 Views
Registered: ‎06-09-2018

jesd sync status

JESD_sysref_drops.PNG

 

I've checked the link settings and they all look correct, but it looks like we're not moving past ILA.

 

Any thoughts?

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Hi .@.@.u.@.@.,

 

what is driving tx_sync low again? Can you find out?

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Observer
Observer
535 Views
Registered: ‎06-09-2018

JESD_SYNC_LOSS_SMALL.PNG

 

I did (much more) work, and I am able to get data out of the DAC - I'm clearly getting past ILA and into the data phase. This is consistent: that is to say the SYNC drops repeatedly at this exact point. 

 

This must be caused by the DAC then - I don't think it could be a setting on the FPGA side - if a setting was wrong, the link should either never work, or be much worse, and I don't think it is a physical connection problem (again, it would never get to the data phase in that case) - am I correct in that? 

 

Can anyone think of something that it could be, or where to best start poking?

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