09-11-2018 06:57 AM
what is driving tx_sync low again? Can you find out?
09-26-2018 12:20 AM
I did (much more) work, and I am able to get data out of the DAC - I'm clearly getting past ILA and into the data phase. This is consistent: that is to say the SYNC drops repeatedly at this exact point.
This must be caused by the DAC then - I don't think it could be a setting on the FPGA side - if a setting was wrong, the link should either never work, or be much worse, and I don't think it is a physical connection problem (again, it would never get to the data phase in that case) - am I correct in that?
Can anyone think of something that it could be, or where to best start poking?