I can normally receive data with ADC through the IP core of jesd204 V7 .1 in Vivado 2016.3, but when I debug with ISE14 .7, the jesd204 IP core check will report errors when I synthesize my program ,and I delete jesd204 IP. Xco file, replaced with. NGC file and. V file, it can generate. bit file, but this IP core can not establish a data link with ADC and can not receive the correct number. the further more jesd204 ip core V3.2 can don't set lane rate ,I don't know how to set this parameter ，The official website could not find this version of the IP 3.2 version user manual . Now I need to debug my ADC chip in ISE 14.7 and ask the teacher to solve this problem. Thank you!