loopback in Aurora 3.0 simplex both?

[confuey]

Is it possible to do GTX loopback tests using a single, Simplex-Both Aurora core?  I am using Aurora 3.0, 10.1 tools, and a Virtex-5 FXT.  I am only using a single lane, 4-byte width.  So far, I am having no luck.

- I am connecting the RX control signal outputs from my Aurora core (RX_ALIGNED, RX_VERIFY, and RX_RESET) back to the TX control inputs of the same core.

- RX_LANE_UP is high.  RX_CHANNEL_UP, TX_LANE_UP, and TX_CHANNEL_UP are all low.

I am relatively new to all this, so any help or suggestions would be appreciated.

[mcgett]

A simplex core is unidirectional.  It can't be looped back on itself.

[lohiya]

Hi, I am doing a similar loop back exercise with Aurora core on a HTG-V5-PCIE development board . 

Aurora version : 4.2

Directivity: Simplex.

flow: Streaming 

Xilinx ISE:11.2  

FPGA: SX95T , virtex 5 

I have generated two simplex aurora cores one as TX and the other with direction  RX. I want to loop back the TX output to the RX inputs and verify this loopback works correctly with by probing RXD lines using chipscope VIO core.

Now, i have created an Aurora_top.vhd in which i instantiate the aurora_TX and aurora_RX. The  entity declaration of the top is as follows:

entity TOP_Level_Aurora is
 
port (
signal reset_top  :in Std_Logic ;
signal clk_P_top  :in Std_Logic ;
signal clk_N_top  :in Std_Logic ;
signal TXP_P_top  :in Std_Logic ;
signal TXP_N_top  :in Std_Logic ;
signal RXP_P_top  :in Std_Logic ;
signal RXN_N_top  :in Std_Logic ;
signal PMA_INIT_top  :in Std_Logic ;
signal INIT_clk_top  :in Std_Logic ;
); 

 However i am not able to get the design working. Since i got it working in simulation i think there is somethign which i am doing wrong in connecting the signals properly to the board i.e. something is wrong with my .UCF file. 

Here is how my UCF file looks like ,

NET INIT_CLK_TOP        LOC="J16";   #50 Mhz Oscillator

################# GTP CLOCK Locations of the pins ###########################

NET "CLK_P_TOP" LOC ="E4";  

NET "CLK_N_TOP" LOC ="D4";

################################ Resets Buttons #################################

NET RESET_TOP           LOC="G27";   #BUTTON

NET RESET_TOP        PULLUP;

NET PMA_INIT_TOP        LOC="H27";   #BUTTON

INST example_design_1_TX /aurora_module_i/gtp_wrapper_i/GTP_TILE_INST/gtp_tile_i LOC=GTP_DUAL_X0Y6;  # since this corressponds to GTP_dual tile 120

Questions>

 Is the UCF correct?  As the user manual of the board mentions that MGT_120 is the GTP_dual connected to the SMA connectors (which i use in this exercise) , i understand that i need to loop back TXP,TXN of transceiver 1  to RXP and RXN respectively of Transceiver 2 , both located in the same GTP_dual (120 or _X0Y6) .

Is this understnading correct or do i have to instantiate in my UCf differently ? 

any Help will be appreciated .

Thanks in advance

[marting · Accepted solution]

A simple thing to check may be with the RESET_TOP button:  is it active low?  Some of the Aurora example designs have the main reset signal as active low, so unless you are holding the corresponding button, the design appears to be inactive.

If this doesn't help, you may want to make sure that the clock is correctly attached to GTP 120, that PLLLKDET is high and that RXBYTEISALIGNED is high.

Hope this helps! 

[lohiya]

I managed to get my loopback set-up running finally . thank for your support marting1 .

--amit