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Contributor
Contributor
2,416 Views
Registered: ‎08-07-2008

need 100G Ethernet subsystem example design

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Hello,

 

I am unable to find the source code for the example design of the cmac_uplus  mentionned in the PG203.

even in vivado 2017.2 the open example design tab is disabled?

Any suggestion?

 

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Xilinx Employee
Xilinx Employee
4,292 Views
Registered: ‎02-06-2013

Re: need 100G Ethernet subsystem example design

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Hi

 

Have you selected the xci file and right clicked to find the Open IP example design.

 

If generated the core in OOC then the option will be enabled once the runs are done.

 

Upload the snapshot if you still don't see the open IP example design option.

Regards,

Satish

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Xilinx Employee
Xilinx Employee
4,293 Views
Registered: ‎02-06-2013

Re: need 100G Ethernet subsystem example design

Jump to solution

Hi

 

Have you selected the xci file and right clicked to find the Open IP example design.

 

If generated the core in OOC then the option will be enabled once the runs are done.

 

Upload the snapshot if you still don't see the open IP example design option.

Regards,

Satish

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------
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Contributor
Contributor
2,394 Views
Registered: ‎08-07-2008

Re: need 100G Ethernet subsystem example design

Jump to solution
I generated the output products and waited until the synthesis of the block to be completed, then i was able to get the files. Thanks for the answer.
Cheers,
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