08-31-2018 03:38 AM
we have designed a custom hardware that contains XC7K410T-2FFG900I fpga and phy (88e1111),we are trying to enable the phy using trimode ethernet mac. we are getting placement error shown below.
"Place:906 - Components driven by IO clock net
<trimac_block/gmii_interface/gmii_rx_clk_bufio> can't be placed and routed
because location constraints are causing the clock region rules to be
violated. IO Clock net <trimac_block/gmii_interface/gmii_rx_clk_bufio> is
being driven by BUFIO <trimac_block/gmii_interface/bufio_gmii_rx_clk> locked
to site "BUFIO_X0Y12" Because of this location contraint,
<trimac_block/gmii_interface/gmii_rx_clk_bufio> can only drive clock region
"CLOCKREGION_X0Y3". The following components driven by
<trimac_block/gmii_interface/gmii_rx_clk_bufio> have been locked to sites
outside of these clock regions:
trimac_block/gmii_rxd_int<7> (Locked Site: ILOGIC_X0Y242 CLOCKREGION_X0Y4)
trimac_block/gmii_rxd_int<6> (Locked Site: ILOGIC_X0Y241 CLOCKREGION_X0Y4)
trimac_block/gmii_rxd_int<5> (Locked Site: ILOGIC_X0Y240 CLOCKREGION_X0Y4)
trimac_block/gmii_rxd_int<4> (Locked Site: ILOGIC_X0Y239 CLOCKREGION_X0Y4)
trimac_block/gmii_rxd_int<3> (Locked Site: ILOGIC_X0Y238 CLOCKREGION_X0Y4)
trimac_block/gmii_rxd_int<2> (Locked Site: ILOGIC_X0Y237 CLOCKREGION_X0Y4)
trimac_block/gmii_rxd_int<1> (Locked Site: ILOGIC_X0Y236 CLOCKREGION_X0Y4)
trimac_block/gmii_rxd_int<0> (Locked Site: ILOGIC_X0Y235 CLOCKREGION_X0Y4)
trimac_block/gmii_rx_er_int (Locked Site: ILOGIC_X0Y171 CLOCKREGION_X0Y3)
trimac_block/gmii_rx_dv_int (Locked Site: ILOGIC_X0Y173 CLOCKREGION_X0Y3)
Please evaluate the location constraints of both the BUFIO and the components
driven by <trimac_block/gmii_interface/gmii_rx_clk_bufio> to ensure that they
follow the clock region rules of the architecture. For more information on
the clock region rules, please refer to the architecture user's guide. To
debug your design with partially routed design, please allow mapper/placer to
finish the execution (by setting environment variable
XIL_PAR_DEBUG_IOCLKPLACER to 1).
ERROR:Pack:1654 - The timing-driven placement phase encountered an error."
here we have connected gmii_rx_clk to bank15 location M18(SRCC pin) and data lines in bank 16.
how to overcome this error? any attributes we can add so that bit stream is generated?pls help
08-31-2018 02:12 PM
The gmii_rx_clk is being fed into the FPGA via the BUFIO which can drive a single I/O clock network in the same region/bank
The gmii_rxd_int<*> are outside of this region. This is why you are seeing this error.
Manually replacing the BUFIO by BUFG may cause this error to go away.
Else you need to put placement constraints such that the BUFIO is in the same region as that of the gmii_rxd_int<*>.
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