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Registered: ‎05-17-2018

"Speed_mode" of IPcore "GMIItoRGMII" does not change depending on the port setting information of the link partner.

I would like to use Ethernet with ZYNQ-7000 SoC and configuration like that in Figure 1.
I would like to generate transmission clock (TXCLK) with IPcore "GMIItoRGMII" and IPcore "ClockingWizard" with the configuration as shown in Figure 2.
However, a problem occurred.


When link partner setting is set to 100BASE-TX or 1000BASE-T, packets can not be sent or received.
The cause of this problem was that speed_mode (internal signal of IPcore "GMIItoRGMII") did not change from 0x00 and TXCLK was fixed at 2.5 MHz.


In order to pursue the cause, I examined several points. (See Figure 3)


1. Link Paeter and PHY perform auto-negotiation.
I checked the PHY register and confirmed that auto-negotiation was completed normally.
I also checked the PHY register and confirmed that the correct Link Partner's Speed / Duplex information is set in the PHY register.


2. The WEC reads the PHY register and sets the link partner's Speed / Duplex information in the PS GEM register.
I checked the PHY register and GEM register and confirmed that the Speed / Duplex information of the correct Link Partner is set in the GEM register.


3. The value of speed_mode is determined by the value of the GEM register.
No matter how you change the speed / duplex information of the link partner, speed_mode will always remain 0x00!


4. The clock frequency of TXCLK is determined by the value of speed_mode.
I forcibly changed the value of speed_mode input to the clock selector buffer (BUFGMUX) and confirmed that the corresponding clock frequency (25 MHz or 125 MHz) is correctly output to TXCLK.
Fix to speed_mode = 0x01: TXCLK = 25 MHz
Fix to speed_mode = 0x10: TXCLK = 125 MHz


From the above point, I think that it is caused by not being able to communicate speed information between PS - PL.
Are there any points to check in order to communicate this information properly?


Thank You.

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