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Participant welcomelm
Participant
477 Views
Registered: ‎01-07-2019

reference design for AXI 1G Ethernet subsystem with 1588 (ptp) support

Hi

Is there a reference design available for AXI 1G Ethernet subsystem with 1588 support?

I have reference design for 10G AXI 1588, but I couldn't get ethernet to ping and I was getting the following error from dmesg

Configuring network interfaces... [    3.828026] xilinx_axienet 80020000.xxv_ethernet eth0: axienet_device_reset: Block lock of XXV MAC didn't getSet cross check the ref clockconfiguration

 On the other hand, I have a reference design for 1G AXI, which is working for me. But that design doesn't have 1588 support.

Thanks a lot

2 Replies
Xilinx Employee
Xilinx Employee
459 Views
Registered: ‎08-15-2018

Re: reference design for AXI 1G Ethernet subsystem with 1588 (ptp) support

Hi @welcomelm,

I've got this 2017.1 example design for PL 1G PTP. To load the design place the IP repo and the tcl script I've attached in the same directory and call the command:

vivado -source all.tcl

sourcePL_PTP_1G.PNG

This is an old design and I haven't had the time to run it through the Linux software stack to double check it all works, but it should be a good starting point for you.

 

Hope this helps!

 

Thanks,

Clayton

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Participant welcomelm
Participant
428 Views
Registered: ‎01-07-2019

Re: reference design for AXI 1G Ethernet subsystem with 1588 (ptp) support

Thanks so much for sharing. Are there any patches for fsbl and bsp?

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