08-02-2017 09:19 PM
i am having a requirement of sending data from an application(in PC) to KC705 board through the SFP interface. when i connected the board part to the block design i got a dialog box like the attached image. I chose the first one ie AXI 1G/2.5G ethernet subsystem and made a design like the attached one. my assumption is that, the data send from PC will be available at FIFO and from there i can use the data. will it work???
I am beginner to the ethernet area. i didnt get any proper document from google. so please help me.
thanks in advance.
08-02-2017 09:37 PM
What is your end application.
Do you have an application running on the processor to process the incoming data or just want to do it in the FPGA logic
You can directly target the example design and use the user interface if you don't need the processor.
Refer PG138 for more info.
Below link has 2.5G design.
Refer below XAPP for SW stack and design.
08-02-2017 10:35 PM
thanks for your response.
i have an application running on my microblaze to process the data.
i am reading this, https://www.xilinx.com/support/answers/65494.html . will it satisfy my requirement if i am having a processor based design?? or i have to use some other design like xapp1026??
i tried the xapp1026 design. but when i tried to ping the board from the pc it shows the message "destination host unreachable."
what can be the problem??
thanks and regards,
08-08-2017 01:52 AM
The reference design in 65494 is standalone design and doesn't suit for processor applications design.
You need to use the Axi subsystem core and can use LWIP stack