07-11-2020 12:06 AM - edited 07-11-2020 12:51 AM
rx_enable and rx_mac_aclk of Tri-mode Ethernet MAC(TEMAC) are kept low, and I cannot receive data from the module.
This is the block design diagram.
This is my development environment.
* OS: Ubuntu 18.04.4 LTS
* Kernel Version: 5.5.0
* Vivado Version: 2020.1
* FPGA Device: KC705
The board jumpers are set properly to operate in GMII mode.
I have verified the board settings with the KC705 echo example of verilog-ethernet.
The project directory and bitstreams are attached below.
* fpga.bit: echo server example of verilog-ethernet to verify the board jumpers are properly set (nc -u 192.168.1.128 1234)
* temac.tgz: project directory
* design_1_wrapper.tgz: bitstream file and debug probes file
07-16-2020 09:11 PM - edited 07-16-2020 09:14 PM
Is this problem related to "the core bring up sequence"?
While reading the manual for "UltraScale+ Devices Integrated 100G Ethernet Subsystem v2.4", I found something like below.
It describes the core bring up sequence.
Do I need a sequence of operations to bring up TEMAC?
I tried to find a similar one from TEMAC, but I couldn't find one.
07-22-2020 06:11 AM
07-22-2020 09:05 PM
I've a quick check on your design. The simulation seems working while the clockin frequency in TestBench should be 200MHz instead of 100MHz.
Then can you add all TEMAC input/output signals into ILA for debugging? Please comparing these signals against those in simulation. Is there any difference?