cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Contributor
Contributor
563 Views
Registered: ‎07-10-2020

rx_enable and rx_mac_aclk of TEMAC are kept low (KC705)

 

rx_enable and rx_mac_aclk of Tri-mode Ethernet MAC(TEMAC) are kept low, and I cannot receive data from the module.

 

This is the block design diagram.

capture.png

waveform.PNG

 

 This is my development environment.

* OS: Ubuntu 18.04.4 LTS
* Kernel Version: 5.5.0
* Vivado Version: 2020.1
* FPGA Device: KC705

 

The board jumpers are set properly to operate in GMII mode.

I have verified the board settings with the KC705 echo example of verilog-ethernet.

 

The project directory and bitstreams are attached below.

* fpga.bit: echo server example of verilog-ethernet to verify the board jumpers are properly set (nc -u 192.168.1.128 1234)

* temac.tgz: project directory

* design_1_wrapper.tgz: bitstream file and debug probes file

 

Tags (4)
0 Kudos
9 Replies
Highlighted
Contributor
Contributor
448 Views
Registered: ‎07-10-2020

 

Additionally, I found that gmii_rx_clk is kept low also.

Does anyone have a solution to this problem?

figure365.PNG

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
406 Views
Registered: ‎05-01-2013

gmii_rx_clk (s_axi_aclk) comes from clk_wiz/clk_out2

So is clk_wiz locked first?

0 Kudos
Highlighted
Contributor
Contributor
393 Views
Registered: ‎07-10-2020

Yes, clk_wiz_locked is set to 1.

0 Kudos
Highlighted
Contributor
Contributor
362 Views
Registered: ‎07-10-2020

Is this problem related to "the core bring up sequence"?

 

While reading the manual for "UltraScale+ Devices Integrated 100G Ethernet Subsystem v2.4", I found something like below.

It describes the core bring up sequence.

 

cmac-usplus-bring-up-1.png

 

 

Do I need a sequence of operations to bring up TEMAC?

I tried to find a similar one from TEMAC, but I couldn't find one.

Tags (1)
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
357 Views
Registered: ‎05-01-2013

I don't think you need it for TEMAC.

Can you see the clock now? Please make sure all the resets released and all the clocks ready first.

0 Kudos
Highlighted
Contributor
Contributor
303 Views
Registered: ‎07-10-2020

Although all reset signals to TEMAC are released, rx_reset (output) of TEMAC is kept high.

Do you have any clue?

0 Kudos
Highlighted
Contributor
Contributor
262 Views
Registered: ‎07-10-2020

@guozhenp  I couldn't find a solution yet.

The key problem is that rx_reset is asserted.

I don't see this problem when I run a simulation.

Do you have any suggestions?

0 Kudos
Highlighted
Contributor
Contributor
257 Views
Registered: ‎07-10-2020

I have attached a block diagram that I have used for simulation and project directory.

temac-diagram.PNG

 

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
213 Views
Registered: ‎05-01-2013

I've a quick check on your design. The simulation seems working while the clockin frequency in TestBench should be 200MHz instead of 100MHz.

Then can you add all TEMAC input/output signals into ILA for debugging? Please comparing these signals against those in simulation. Is there any difference?

0 Kudos