09-12-2014 06:36 AM
Hi to all.
I'm working with Aurora 8b/10b using some Viretx5 devices.
I'm interconneting multiple devices using a simplex solution.
Sometime i need to risincronize the devices resetting the Tx module of Aurora Core.
There is another way with less impact in the Aurora structure that is possible to use to resend the sync phase?
Tks to all.
09-12-2014 09:03 PM
You shouldn't have to resend the sync word as the protocol has periodic clock correction words to keep the channel in sync. If you are working with the provided example with the core, there's a component that counts and when it reaches a predetermined value, it stobes the DO_CC port on the Aurora core. You may need to adjust this count to generate clock correction words more often. Note that this will decrease your channel bandwidth but should make the link more tolerable to clock jitter. I found that when I was communicating between two Virtex 6 parts on two separate boards from a vendor with independent reference clocks and a data rate of 5 Gbps, I needed to perform clock corrections roughly every 1000 user clock cycles to maintain the link. This was dependent upon the quality of the reference clock and the data rate. Lower data rates required less frequent clock corrections.
09-16-2014 03:00 AM
Hi Jordan, tks for your reply but probably my question was badly posed.
My application doesen't use clock recovery.
The syncronization words was the comma that are used for alignement in the receiver lane initialization, in fact using a simplex architecture if the receiver starts before the transmitter i should resend comma initialization words.
Another question :
I have two subsystems connected by Optical Link. The clocks of each subsystems are locked with a high precison 10 Mhz clock. It is possible to lock the recovered clock of CDR always with the same phase?
In fact when i restart the system the data are sometime shifted for a period of system clock.
Tks for your attention
09-16-2014 03:49 AM