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olivierporchy
Contributor
Contributor
424 Views
Registered: ‎06-18-2019

syntax error IP 10G/25G Ethernet

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Dear all

I have a syntax error in 10G/25G Ethernet when synthetizing.

olivierporchy_0-1627482206673.png

The same IP synthetized in a Vivado 2020.1 design is OK.

Could you please give me assistance ?

Regards

Olivier

 

1 Solution

Accepted Solutions
guozhenp
Xilinx Employee
Xilinx Employee
145 Views
Registered: ‎05-01-2013

This error is fixed in 2021.2

View solution in original post

9 Replies
guozhenp
Xilinx Employee
Xilinx Employee
370 Views
Registered: ‎05-01-2013

Try generating the IP example design

Does the example have the same error?

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olivierporchy
Contributor
Contributor
268 Views
Registered: ‎06-18-2019

Hi

Sorry for the delay to answer, i was in hollydays.

The example design have the same error with Vivado 2021.1 (no error with Vivado 2020.1).

Regards

Olivier

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guozhenp
Xilinx Employee
Xilinx Employee
264 Views
Registered: ‎05-01-2013

Even the IP example design has the error?

Please provide the details, e.g. deveice family, IP configurations in every GUI page.

Or just upload the IP .xci file.

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olivierporchy
Contributor
Contributor
248 Views
Registered: ‎06-18-2019

Hi

Please find xci file attached.

Regards

Olivier

 

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guozhenp
Xilinx Employee
Xilinx Employee
243 Views
Registered: ‎05-01-2013

I check the attached .xci file. It doesn't look like IP core configurations.

Please let me know all the settings you've changed in the IP core GUI.

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olivierporchy
Contributor
Contributor
237 Views
Registered: ‎06-18-2019

Please try with the attached xci file

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guozhenp
Xilinx Employee
Xilinx Employee
177 Views
Registered: ‎05-01-2013

OK. I can see the error.

I created a new CR-1109486. It may take some time to fix it.

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guozhenp
Xilinx Employee
Xilinx Employee
146 Views
Registered: ‎05-01-2013

This error is fixed in 2021.2

View solution in original post

olivierporchy
Contributor
Contributor
100 Views
Registered: ‎06-18-2019

Hi

Fine, thank you!

Olivier

 

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