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Visitor
Visitor
315 Views
Registered: ‎12-26-2017

the SGMII link is low sometimes in vivado2019.1

HI,

i am using the SGMII ip and a hardware PHY (88E1111, marvell) to create a ethernet solution, the vivado is vivado 2019.1 and the FPGA is the V7 690T,
it works ok when i use the JTAG
to debug, but when i download the .bin file to the flash, and disconnect the JTAG, sometimes it cannot work , and the
status_vector[0], that is the link of the SGMII, is low, at this time , if i restart the device , or i put the reset button
to reset the whole device, it works ok ,the link of the SGMII, goes to high. so what is the problem ? i donot know what is
the key point.

thank you!

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7 Replies
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Moderator
Moderator
262 Views
Registered: ‎08-25-2009

Re: the SGMII link is low sometimes in vivado2019.1

Hi @zhipengzhao ,

It looks like this issue is related to the way how you configure the board.

I would firstly check if the clocking is stable once the .bin is programmed into the flash. Thus a subsequent reset is needed to bring the link up.

 

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Highlighted
Visitor
Visitor
254 Views
Registered: ‎12-26-2017

Re: the SGMII link is low sometimes in vivado2019.1

HI nanz,

thank you!

i checked that the clock is stable , and i try to set the clock to 12Mhz or 9Mhz ,but it also happens .now i think it works  unnormal once in 10 times i test.

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Visitor
Visitor
103 Views
Registered: ‎12-26-2017

Re: the SGMII link is low sometimes in vivado2019.1

is there some suggestions for me? hope to get suggestions from you, thanks!

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Moderator
Moderator
78 Views
Registered: ‎08-25-2009

Re: the SGMII link is low sometimes in vivado2019.1

HI @zhipengzhao ,

What is this 12MHz and 9MHz clock? SGMII needs 125MHz clock.

Is a reset help to bring up the link once the SGMII link is down?

"Don't forget to reply, kudo and accept as solution."
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Highlighted
Visitor
Visitor
59 Views
Registered: ‎12-26-2017

Re: the SGMII link is low sometimes in vivado2019.1

HI, nanz, thank you!

the 12MHz and 9MHz clock is the SPI clock for program. the 125MHz clock for SGMII is ok , because there are more than eight sgmii IP in my design ,they shared the 125M reference clock , and only one or two sgmii links down every time , at the same time others link up . a reset can not bring up the link once the SGMII link is down, so i am confused.

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Xilinx Employee
Xilinx Employee
46 Views
Registered: ‎05-01-2013

Re: the SGMII link is low sometimes in vivado2019.1

If the extra reset is always helpful, you can just create a protect logic in your design that do reset automatically after the timeout that the link is still down.

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Visitor
Visitor
34 Views
Registered: ‎12-26-2017

Re: the SGMII link is low sometimes in vivado2019.1

HI , 

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