03-23-2020 08:37 PM
i am using the SGMII ip and a hardware PHY (88E1111, marvell) to create a ethernet solution, the vivado is vivado 2019.1 and the FPGA is the V7 690T,
it works ok when i use the JTAG
to debug, but when i download the .bin file to the flash, and disconnect the JTAG, sometimes it cannot work , and the
status_vector, that is the link of the SGMII, is low, at this time , if i restart the device , or i put the reset button
to reset the whole device, it works ok ,the link of the SGMII, goes to high. so what is the problem ? i donot know what is
the key point.
03-25-2020 01:47 AM
Hi @zhipengzhao ,
It looks like this issue is related to the way how you configure the board.
I would firstly check if the clocking is stable once the .bin is programmed into the flash. Thus a subsequent reset is needed to bring the link up.
03-25-2020 02:49 AM
i checked that the clock is stable , and i try to set the clock to 12Mhz or 9Mhz ,but it also happens .now i think it works unnormal once in 10 times i test.
07-01-2020 10:20 AM
07-01-2020 06:20 PM
HI, nanz, thank you!
the 12MHz and 9MHz clock is the SPI clock for program. the 125MHz clock for SGMII is ok , because there are more than eight sgmii IP in my design ,they shared the 125M reference clock , and only one or two sgmii links down every time , at the same time others link up . a reset can not bring up the link once the SGMII link is down, so i am confused.
07-01-2020 08:37 PM
If the extra reset is always helpful, you can just create a protect logic in your design that do reset automatically after the timeout that the link is still down.
07-01-2020 11:13 PM