05-20-2012 07:44 AM
when I used the IP AURORA V5.2 ,in the map operation,there are two problems
constraintsystem:58-constraint<NET "*/rsest_logic_i/init_clk_i" TNM_NET = INIT_clk;> [auroractrl_top.ucf(78)]:NET "*/rsest_logic_i/init_clk_i" doesnot match any design objects
then in the ucf file, I did the things,for example #NET "*/rsest_logic_i/init_clk_i" TNM_NET = INIT_clk.
I meet the another problem
ERROR:PACK:1654 - the timing-drivern placement phase encountered an error
place:990-Unroutable placement! A GT/OPAD component pair have been found that are not placed at a rountable GT/OPAD site pair.The GT component <aurora/aurora_8b10b_v5_2_example_design_bak/aurora_module_i/gtp_wrapper_i/GTP_TILE_INST/gtp_tile_i> is placed at site <OPAD_x0y16>. the GT<TXN0)> pin can route to the OPAD only if the load component is placed at an offset of (3 -1) with respect to the driver component. this placement is UNROUTABLE in PAR and therefore , this error condition should be fixed in your design . You may use the clock_DEDICATED_ROUTE constraint ini the ucf file to demote this message to a WARNING in order to generate an NCD file. The NCD file can then be used in FPGA EDITOR to deburg the problem. A list of all the comp PINS used in this clock placement rule is listed below. these examples can be uesd directly in the ucf file to demote this error to a WARNING
<PIN "aurora/aurora_8b10b_v5_2_example_design_bak/aurora_module_i/gtp_wrapper_i/GTP_TILE_INST/gtp_tile_i.TXN0" clock_DEDICATED_ROUTE = FALSE;> <PIN"B_TD_N_OBUF.I" clock_DEDICATED_ROUTE = FALSE>
BUT when I don't defined the pins with AURORA TXN TXP RXN RXP in the FPGA, ERROR would disappear.
SO could U help me how to do it
05-22-2012 03:43 AM