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2,503 Views
Registered: ‎11-27-2008

the error in the IP : AURORA V5.2 in the V5 FPGA

when I used the IP AURORA V5.2 ,in the map operation,there are two problems

first:

 constraintsystem:58-constraint<NET "*/rsest_logic_i/init_clk_i" TNM_NET = INIT_clk;> [auroractrl_top.ucf(78)]:NET "*/rsest_logic_i/init_clk_i"  doesnot match any design objects

 

then in the ucf file, I did the things,for example  #NET "*/rsest_logic_i/init_clk_i" TNM_NET = INIT_clk.

I meet the another problem

 

ERROR:PACK:1654 - the timing-drivern placement phase encountered an error

place:990-Unroutable placement! A GT/OPAD component pair have been found that are not placed at a rountable GT/OPAD site pair.The GT component <aurora/aurora_8b10b_v5_2_example_design_bak/aurora_module_i/gtp_wrapper_i/GTP_TILE_INST/gtp_tile_i> is placed at site <OPAD_x0y16>. the GT<TXN0)> pin can route to the OPAD only if the load component is placed at an offset of (3 -1) with respect to the driver component. this placement is UNROUTABLE in PAR and therefore , this error condition should be fixed in your design . You may use the clock_DEDICATED_ROUTE constraint ini the ucf file to demote this message to a WARNING in order to generate an NCD file. The NCD file can then be used in FPGA EDITOR to deburg the problem. A list of all the comp PINS used in this clock placement rule is listed below. these examples can be uesd directly in the ucf file to demote this error to a WARNING

<PIN "aurora/aurora_8b10b_v5_2_example_design_bak/aurora_module_i/gtp_wrapper_i/GTP_TILE_INST/gtp_tile_i.TXN0" clock_DEDICATED_ROUTE = FALSE;> <PIN"B_TD_N_OBUF.I" clock_DEDICATED_ROUTE = FALSE>

 

BUT when I don't defined the pins with AURORA TXN TXP RXN RXP in the FPGA, ERROR would disappear.

SO could U help me how to do it

THANGK U!!

 

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Teacher
Teacher
2,489 Views
Registered: ‎09-09-2010

Regarding init_clk, synthesis may have renamed this to the clock that is driving it. You could add a KEEP constraint, but probably not worth bothering with.

We are constraining the pins, rather than the tiles. This seems to work well enough in ISE 12.* and ISE 13.*.

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"If it don't work in simulation, it won't work on the board."
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