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Visitor
Visitor
3,791 Views
Registered: ‎08-17-2016

timing diagram for binary counter v12

Hi all,

 

I need a loadable binary counter. I use the IP v12.

It is not clear to me how to setup the counter when CE used.

Is there a timing diagram availabe which shows the behaviour of the core

with respect to CE, LOAD, CLK, L[], Q[]??

 

Thanks Emi

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Moderator
Moderator
3,663 Views
Registered: ‎02-16-2010

Can you simulate the core and check?
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Xilinx Employee
Xilinx Employee
3,491 Views
Registered: ‎02-06-2013

Hi

 

Refer below doc which has the info on how to control the signals

 

http://www.xilinx.com/support/documentation/ip_documentation/c_counter_binary/v12_0/pg121-c-counter-binary.pdf

Regards,

Satish

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