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Observer ammadali90
Observer
332 Views
Registered: ‎08-23-2015

timing violation in Ethernet subsystem

Hi,

I have a design which composes of 4 Ethernet subsystem MAC with RGMI interfaces. The Ethernet subsystem has GTX pin if I connect this pin to an external clock of 125 MHz in ZCU102 board the design works completly fine.

I don't want to use this external clock source for some reason, I want to drive the GTX pin from Zynq PS (external PL clock). But in that case I got setup timing violation.

Attached is the pdf of design and also the constraints suggested by AR#65947. 

BR,

Ammad Ali

 

 

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4 Replies
Visitor shanep1
Visitor
320 Views
Registered: ‎08-24-2018

Re: timing violation in Ethernet subsystem


@ammadali90 wrote:

Hi,

I have a design which composes of 4 Ethernet subsystem MAC with RGMI interfaces. The Ethernet subsystem has GTX pin if I connect this pin to an external clock of 125 MHz in ZCU102 board the design works completly fine.

I don't want to use this external clock source for some reason, I want usps tracking to drive the GTX pin from Zynq PS (external PL clock). But in that case I got setup timing violation.

Attached is the pdf of design and also the constraints suggested by AR#65947. 

BR,

Ammad Ali

 

 


Yeah need help with this too.

Thanks in advance.

Regards,

Shane

________________________________________________________________________

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Xilinx Employee
Xilinx Employee
266 Views
Registered: ‎05-01-2013

回复: timing violation in Ethernet subsystem

What's the timing errors?

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Observer ammadali90
Observer
238 Views
Registered: ‎08-23-2015

回复: timing violation in Ethernet subsystem

Hi,

I have attached the Path report summary which has WNS.

BR,

Ammad Ali

1.png
schematic.png
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Observer ammadali90
Observer
206 Views
Registered: ‎08-23-2015

回复: timing violation in Ethernet subsystem

Hi,
I have attached the Path report summary!
Is it ok?
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