cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Observer
Observer
433 Views
Registered: ‎08-23-2015

timing violation in Ethernet subsystem

Hi,

I have a design which composes of 4 Ethernet subsystem MAC with RGMI interfaces. The Ethernet subsystem has GTX pin if I connect this pin to an external clock of 125 MHz in ZCU102 board the design works completly fine.

I don't want to use this external clock source for some reason, I want to drive the GTX pin from Zynq PS (external PL clock). But in that case I got setup timing violation.

Attached is the pdf of design and also the constraints suggested by AR#65947. 

BR,

Ammad Ali

 

 

0 Kudos
4 Replies
Highlighted
Visitor
Visitor
421 Views
Registered: ‎08-24-2018


@ammadali90 wrote:

Hi,

I have a design which composes of 4 Ethernet subsystem MAC with RGMI interfaces. The Ethernet subsystem has GTX pin if I connect this pin to an external clock of 125 MHz in ZCU102 board the design works completly fine.

I don't want to use this external clock source for some reason, I want usps tracking to drive the GTX pin from Zynq PS (external PL clock). But in that case I got setup timing violation.

Attached is the pdf of design and also the constraints suggested by AR#65947. 

BR,

Ammad Ali

 

 


Yeah need help with this too.

Thanks in advance.

Regards,

Shane

________________________________________________________________________

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
367 Views
Registered: ‎05-01-2013

What's the timing errors?

0 Kudos
Highlighted
Observer
Observer
339 Views
Registered: ‎08-23-2015

Hi,

I have attached the Path report summary which has WNS.

BR,

Ammad Ali

1.png
schematic.png
0 Kudos
Highlighted
Observer
Observer
307 Views
Registered: ‎08-23-2015

Hi,
I have attached the Path report summary!
Is it ok?
0 Kudos