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Visitor
Visitor
3,316 Views
Registered: ‎12-20-2010

ucf is wrong for srio

Hi , Xilinx Experts :

 

 I am disappointed to find out the ucf is wrong when I use "core generator " to gerenate srio ip at ISE 13.3

 

The device listed at the ucf does not match the one I choosed at the core generator project. The "LOC" Constraints does not match the actual device either . I would like to know if XILINX is going to release a patch for this srio core generator ?

 

If not , can I choose GTPs for my x4 lanes application myself ? Which rules should I stick to when picking up two GTX_DUAL tiles ? And which tile I should use to hook up the differential clock ( sys_clk ) to ? And which tile should be the " Lane 0 & 1" for my SRIO x4 lanes ?

 

Thankyou and Merry Christmas !

 

 

 

Zhao

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2 Replies
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Scholar
Scholar
3,308 Views
Registered: ‎02-03-2010

Re: ucf is wrong for srio

Hi zhao,

 

The .ucf file is generated for example design. It will not change for every device you choose for automatically.

When you are using it for another device, you have to modify yourself.

 

Regards,

Koti Reddy

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Visitor
Visitor
3,305 Views
Registered: ‎12-20-2010

Re: ucf is wrong for srio

Hi , Koti :

 

Thankyou for your reply :)

 

Could you please tell me which rules ( or which documents ) should I stick to when picking up two GTX_DUAL tiles ?  And which tile should be the " Lane 0 & 1" for my SRIO x4 lanes ?

 

Merry Christmas !

 

 

Zhao

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