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123 Views
Registered: ‎08-15-2017

using axi_ethernet to configure a phy chip, which is the fhostclk of the MDC of MII Management (MDIO) ?

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the fhostclk of the MDC of MII Management (MDIO) in the green box in the figuer should be CLKOUT2,  right or not?

xps1.png

 

 

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Moderator
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Registered: ‎08-25-2009

Re: using axi_ethernet to configure a phy chip, which is the fhostclk of the MDC of MII Management (MDIO) ?

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Hi @microchip_zhang ,

MDC clock is the output clock from the MAC core to the PHY interface and upto 2.5MHz. Why are you questioning the clock? What is the issue you have?

 

"Don't forget to reply, kudo and accept as solution."

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Moderator
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Registered: ‎08-25-2009

Re: using axi_ethernet to configure a phy chip, which is the fhostclk of the MDC of MII Management (MDIO) ?

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Hi @microchip_zhang ,

MDC clock is the output clock from the MAC core to the PHY interface and upto 2.5MHz. Why are you questioning the clock? What is the issue you have?

 

"Don't forget to reply, kudo and accept as solution."

View solution in original post

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