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prachojain
Contributor
Contributor
9,789 Views
Registered: ‎04-25-2014

vc707 problem with SFP+

Hello everyone

                    I am trying to perform loop back on vc707 board. So for that I have written the code whereby my user logic block will generate the data after the core status 0th bit gets high. but the problem I am facing is that I am not getting any signal on tx line (I check through tester) even though I am giving proper clock freq of 156.25 MHz  through AL34 and ak34 to Si5324. and also as describe in LogiCORE IP 10-Gigabit Ethernet PCS/PMA v4.1 page 20 I have connect the output of drp to input of drp port and drp_req to drp_gnt.. I am not getting any signal on tx line.

I have made for the core
  tx_fault          <= '0';
  signal_detect     <= '1';
  prtad             <= "00000";
  drp_gnt           <=drp_req;
  drp_den_i         <= drp_den_o;
  drp_dwe_i         <= drp_dwe_o;
  drp_daddr_i       <= drp_daddr_o;
  drp_di_i          <= drp_di_o;
  drp_drdy_i        <=  drp_drdy_o;
  drp_drpdo_i       <= drp_drpdo_o;

sfp_tx_disable <= '0';

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5 Replies
prachojain
Contributor
Contributor
9,749 Views
Registered: ‎04-25-2014

Also I am getting the iresetdone high

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prachojain
Contributor
Contributor
9,744 Views
Registered: ‎04-25-2014

core_status[7:0] are all low.

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yenigal
Xilinx Employee
Xilinx Employee
9,737 Views
Registered: ‎02-06-2013

 

Hi

 

Have  you checked the basic debuggings checks mentioned in PG068 and PG072.

 

Are you seeing any local or remote fault conditions.

 

Which loop back option have you enabled and are you seeing sync bytes.

 

Can you attach the captures of status vector and data signals.

Regards,

Satish

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reatingwu
Visitor
Visitor
9,569 Views
Registered: ‎09-18-2014

Dear Sir,

 

  I try to generate DS_TRX_exdes for SFP application, as follows:

  and use chipscope to check the waveform, 

  Find that even no SFP optical signal input, the exdes still output receive data(rx_dat_r ) to frame_check module,

  which is not found in simulation !!

  what's wrong with the design ?

  can someone to give suggestion !

  Thanks ~

   

  DS_TRX_exdes_issue.jpg


DS_TRX_exdes #
(
.EXAMPLE_SIM_GTRESET_SPEEDUP ("TRUE"), // Speedup is turned on for simulation
.EXAMPLE_SIMULATION (1),
.EXAMPLE_USE_CHIPSCOPE (0) //1 - use chipscope to drive resets,
//0 - drive resets from top level ports
)
DS_TRX_exdes_i
(
.Q0_CLK1_GTREFCLK_PAD_N_IN (Q0_CLK1_GTREFCLK_PAD_N_IN),
.Q0_CLK1_GTREFCLK_PAD_P_IN (Q0_CLK1_GTREFCLK_PAD_P_IN),
.SYSCLK_IN (CLK200),
.CLK155R (CLK155),
.TRACK_DATA_OUT (TRACK_DATA_OUT),
.RXN_IN (RXN_IN),
.RXP_IN (RXP_IN),
.TXN_OUT (TXN_OUT),
.TXP_OUT (TXP_OUT)
);

 

 

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yenigal
Xilinx Employee
Xilinx Employee
9,560 Views
Registered: ‎02-06-2013

 

Hi

 

Don't post on threads which are completely different from your issue.

 

Always open a new topic for your issue.

Regards,

Satish

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