08-19-2014 10:18 PM
I am trying to perform loop back on vc707 board. So for that I have written the code whereby my user logic block will generate the data after the core status 0th bit gets high. but the problem I am facing is that I am not getting any signal on tx line (I check through tester) even though I am giving proper clock freq of 156.25 MHz through AL34 and ak34 to Si5324. and also as describe in LogiCORE IP 10-Gigabit Ethernet PCS/PMA v4.1 page 20 I have connect the output of drp to input of drp port and drp_req to drp_gnt.. I am not getting any signal on tx line.
I have made for the core
tx_fault <= '0';
signal_detect <= '1';
prtad <= "00000";
drp_den_i <= drp_den_o;
drp_dwe_i <= drp_dwe_o;
drp_daddr_i <= drp_daddr_o;
drp_di_i <= drp_di_o;
drp_drdy_i <= drp_drdy_o;
drp_drpdo_i <= drp_drpdo_o;
sfp_tx_disable <= '0';
08-25-2014 03:58 AM
Have you checked the basic debuggings checks mentioned in PG068 and PG072.
Are you seeing any local or remote fault conditions.
Which loop back option have you enabled and are you seeing sync bytes.
Can you attach the captures of status vector and data signals.
09-18-2014 02:37 AM
I try to generate DS_TRX_exdes for SFP application, as follows:
and use chipscope to check the waveform,
Find that even no SFP optical signal input, the exdes still output receive data(rx_dat_r ) to frame_check module,
which is not found in simulation !!
what's wrong with the design ?
can someone to give suggestion !
.EXAMPLE_SIM_GTRESET_SPEEDUP ("TRUE"), // Speedup is turned on for simulation
.EXAMPLE_USE_CHIPSCOPE (0) //1 - use chipscope to drive resets,
//0 - drive resets from top level ports
09-18-2014 05:32 AM
Don't post on threads which are completely different from your issue.
Always open a new topic for your issue.