02-23-2019 02:17 AM - edited 02-25-2019 12:15 AM
I am using vcu108 evaluation board. This board has 1 x QSFP28 and 1 x CFP2. I configured Xilinx Ultrascale 25G Ethernet Subsystem IP core (4 lines x 25.7812G) individually for both cfp2 and qsfp and use Finisar 100G transceivers (10km, QSFP28 and CFP2) for my tests:
1- I connected the IP core which was configured for CFP2 to a custom design. Basically, the design injects traffic internally (from FPGA side) to the cfp2. First, I used one board with external loopback (Fig1). Everything worked fine and I received the traffic. Then, I tried board to board communication (Fig2). But I don't receive the data on the second board!
2- I repeated the same test this time with QSFP28 IP core. Both one board loopback and board to board communication worked perfectly.
Regarding the CFP2 test, when one board loopback works and board to board doesn't, the issue should be synchronisation. Could you please advise me how to resolve this issue?
I would greatly appreciate if someone from Xilinx answer my query.
03-05-2019 05:01 AM
Ensure that the polarities of the txn/txp and rxn/rxp lines are not reversed.
If the positive and negative signals of a differential pair are swapped, then data cannot be correctly received on that lane.
Kindly verify that the link has the correct polarity of each differential pair.
Kindly monitor the stat_rx_block_lock this signal indicates that the receiver has detected and locked to the word boundaries as defined by a 01 or 10 control or data header.
This is the first step to ensure that the Ethernet IP is functioning normally.
03-05-2019 09:16 AM
03-05-2019 11:17 PM
I just wanted to check with you on reference clock.
Could you confirm 161.13 MHz as reference clock.
03-08-2019 01:00 AM
03-08-2019 03:24 AM